Memory system for restraining threshold variation to improve data reading
AssigneeKioxia Corporation
InventorsMasanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
Life of this patent
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AssigneeKioxia Corporation
InventorsMasanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
Estimating the term…
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
A semiconductor memory comprising:
A method of controlling a semiconductor memory including a first block, a plurality of first word lines and a plurality of first transistors, the first block including a plurality of first memory cells, the plurality of first word lines being coupled to the first memory cells, the plurality of first transistors being capable of coupling the plurality of first word lines to a plurality of first signal lines, the method comprising:
Dependencies are inferred from the claim text.