US 11,238,935 B2Granted

Semiconductor memory device

AssigneeKioxia Corporation

InventorXu Li

Life of this patent

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Abstract

A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a semiconductor substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction;
a well region formed on a surface layer of the semiconductor substrate;
a source line formed on the well region of the surface layer of the semiconductor substrate;
a first select gate line stacked above the well region in a third direction orthogonal to the first direction and the second direction;
a plurality of word lines stacked above the first select gate line in the third direction;
a second select gate line stacked above the plurality of word lines in the third direction;
a plurality of bit lines disposed above the second select gate line in the third direction and extending in the first direction;
a memory cell array including a plurality of memory strings extending in the third direction and connected between corresponding bit lines and the source line;
a well voltage control circuit configured to control a voltage to be applied to the well region;
a source voltage control circuit configured to control a voltage to be applied to the source line;
and
a row decoder that is controlled to apply a voltage to the first select gate line, the plurality of word lines, and the second select gate line, wherein
before writing data to a selected memory cell in the memory cell array:
the row decoder is controlled to:
at a first timing, apply a voltage to the first select gate line, a selected word line which is one of the word lines connected to the selected memory cell, and a word line disposed in a layer between the selected word line and the well region, to turn on transistors connected thereto,
at a second timing after the first timing, change the voltage applied to the first select gate line to turn off the transistor to which the first select gate line is connected, and
at a third timing after the second timing, change the voltage applied to the selected word line and the word line disposed between the selected word line and the well region to turn off the transistors connected thereto;
the source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing;
and
the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.

17 more elements

A method of performing a write operation on a memory cell of a semiconductor memory device that includes:

a semiconductor substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction;
a well region formed on a surface layer of the semiconductor substrate;
a source line formed on the well region of the surface layer of the semiconductor substrate;
a first select gate line stacked above the well region in a third direction orthogonal to the first direction and the second direction;
a plurality of word lines stacked above the first select gate line in the third direction;
a second select gate line stacked above the plurality of word lines in the third direction;
a plurality of bit lines disposed above the second select gate line in the third direction and extending in the first direction;
a memory cell array including a plurality of memory strings extending in the third direction and connected between corresponding bit lines and the source line, one of the memory strings including the memory cell;
a well voltage control circuit configured to control a voltage to be applied to the well region;
a source voltage control circuit configured to control a voltage to be applied to the source line;
and
a row decoder that is controlled to apply a voltage to the first select gate line, the plurality of word lines, and the second select gate line,
wherein the write operation includes a precharge period and a program period after the precharge period, said method comprising:
at a first timing, applying a voltage to the first select gate line, a selected word line which is one of the word lines connected to the selected memory cell, and a word line disposed in a layer between the selected word line and the well region, to turn on transistors connected thereto;
at a second timing after the first timing, changing the voltage applied to the first select gate line to turn off the transistor to which the first select gate line is connected;
at a third timing after the second timing, changing the voltage applied to the selected word line and the word line disposed between the selected word line and the well region to turn off the transistors connected thereto;
applying a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing;
applying the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing;
and
applying a ground voltage to the well region at a sixth timing that is after the fifth timing.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/010,564Filed 2 Sep 2020
Priority: JP JP2020-04794618 Mar 2020
Published: US 2021/0295916 A123 Sep 2021
Granted: 1 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits