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US 11,238,930 B2Granted
Method of RRAM WRITE ramping voltage in intervals
AssigneeHefei Reliance Memory Limited
InventorsBrent Haukness, Zhichao Lu
Life of this patent
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Abstract
Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.
Claims17
A method, comprising:
- ramping a voltage applied to a bitline or a source line that is coupled to a resistive random access memory (RRAM) cell, from a minimum voltage value to a maximum voltage value during a first time interval, wherein the voltage is for setting or resetting the RRAM cell during a set or rest operation;
- holding the voltage at the maximum voltage value during a second time interval after the first time interval;
- ceasing applying the voltage after the second time interval;
- and
- adjusting a first adjustable current limit of a current that is applied to the source line to be lower than a second adjustable current limit of a current that is applied to the bitline.
2 more elements
Dependencies are inferred from the claim text.