Semiconductor memory device and memory system

A method for controlling a semiconductor memory device, the semiconductor memory device including (i) a first memory cell capable of storing at least 2-bit data, the at least 2-bit data corresponding to one of at least four levels of threshold voltages, and the at least four levels of threshold voltages comprising a first level, a second level higher than the first level, a third level higher than the second level, and a fourth level higher than the third level, and (ii) a word line connected to the first memory cell, and the method comprising:

• writing the at least 2-bit data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, while performing a plurality of program operations and a plurality of verify operations, each program operation including applying a program voltage to the word line, and each verify operation including applying a read voltage lower than the program voltage,
• wherein:
• the plurality of program operations comprise a program operation for the second level, a program operation for the third level, and a program operation for the fourth level, and
• the plurality of verify operations comprise a verify operation for the second level, and do not comprise a verify operation for the third level and a verify operation for the fourth level.

A semiconductor memory device, comprising:

• a plurality of memory cell transistors each capable of storing data of a plurality of bits depending on which one of a plurality of states a threshold voltage is included in, the memory cell transistors being configured to store first data if the threshold voltage is included in a first state, and the memory cell transistors being configured to store second data if the threshold voltage is included in a second state higher than the first state;
• a word line connected to the plurality of memory cell transistors;
• a plurality of bit lines respectively connected to the plurality of memory cell transistors;
• and
• a controller capable of executing a write operation including repeating a program loop including a program operation and a verify operation,
• wherein:
• a verify low voltage and a verify high voltage are set in the first state, and
• the controller is configured to:
• perform the verify operation for each state of write destinations such that a memory cell transistor having a threshold voltage determined to be lower than or equal to the verify low voltage is set to a first program target, a memory cell transistor having a threshold voltage determined to be exceeding the verify low voltage and lower than or equal to the verify high voltage is set to a second program target, and a memory cell transistor having a threshold voltage determined to be exceeding the verify high voltage is set to a program-inhibited target,
• perform the program operation such that while a program voltage is applied to the word line, a first voltage is applied to the bit line connected to the memory cell transistor as the first program target, a second voltage higher than the first voltage is applied to the bit line connected to the memory cell transistor as the second program target, and a third voltage higher than the second voltage is applied to the bit line connected to the memory cell transistor as the program-inhibited target, and
• in response to a number of the memory cell transistors having a threshold voltage lower than the verify low voltage becoming lower than or equal to a first value in the verify operation for the first state, execute the verify operation for the second state in a next program loop.