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US 11,238,923 B2Granted
Memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus Lu
Life of this patent
Estimating the term…
Abstract
A memory device is provided. The memory device includes a cell array having a plurality of cells, each of the plurality of cells operative to store a bit value. The memory device further includes a reset circuit connected to the cell array. The reset circuit is operative to reset, in parallel, the bit value stored in each of the plurality of cells to a predetermined bit value.
Claims20
A memory device comprising:
- a cell array comprising a plurality of cells, each of the plurality of cells operative to store a bit value;
- and
- a reset circuit connected to the cell array, wherein the reset circuit is operative to reset, in parallel, the bit value stored in each of the plurality of cells to a predetermined bit value, wherein the reset circuit comprises a reset signal generator circuit operative to generate a reset signal, and wherein the reset signal is operative to trigger resetting, in parallel, of the bit value stored in each of the plurality of cells to the predetermined bit value.
A memory device comprising:
- a cell array comprising a plurality of cells, each of the plurality of cells operative to store one bit value;
- a power control circuit operative to generate a first signal indicating an initiation of a power up duration of the plurality of cells and a second signal indicating a completion of the power up duration of the plurality of cells;
- and
- a reset circuit operative to reset, in parallel, the bit value stored in each of the plurality of cells to a predetermined bit value during the power up duration.
1 more element
A method of resetting a memory device, the method comprising:
- generating a reset signal as a logical disjunction of a first signal indicating an initiation of a power up duration of a plurality of cells and a second signal indicating a completion of the power up duration of the plurality of cells of a memory device;
- and
- triggering, through the reset signal, a reset of a bit value stored in each of a plurality of cells of a cell array of a memory device to a predetermined bit value in parallel during the power up duration.
Dependencies are inferred from the claim text.