Circuit structure for in-memory computing

A circuit structure for in-memory computing, comprising:

• a plurality of eight-transistor SRAMs, wherein each of the eight-transistor SRAMs comprises two groups of read/write dual ports, two word line ports and two direction configuration ports, wherein data of a first read/write port and data of a second read/write port of each group of the read/write dual ports are inverse of each other;
• a first bit line, connected to a first processor, and connected to the first read/write port of a first group of read/write dual ports of each eight-transistor SRAM in a row direction;
• a second bit line, connected to the second read/write port of the first group of read/write dual ports of each eight-transistor SRAM in the row direction;
• a third bit line, connected to a second processor, and connected to the first read/write port of a second group of read/write dual ports of each eight-transistor SRAM;
• a fourth bit line, connected to the second read/write port of the second group of read/write dual ports of each eight-transistor SRAM in the row direction;
• a first word line, connected to the first processor, and connected to a first word line port of each eight-transistor SRAM;
• a second word line, connected to the second processor, and connected to a second word line port of each eight-transistor SRAM;
• and
• a direction configuration circuit, connected to each direction configuration ports of each eight-transistor SRAM, configured to activate any one of the direction configuration ports of each eight-transistor SRAM to perform a logic operation on the eight-transistor SRAMs in a corresponding direction.