Packaged integrated circuit memory devices having enhanced on-die-termination circuits therein and methods of operating same

A memory package, comprising:

• a package substrate having a plurality of pads thereon;
• a first memory device mounted on the package substrate, and comprising first on-die-termination (ODT) resistance and a first ODT circuit, which determines a value of the first ODT resistance, wherein the first ODT circuit sets the first ODT resistance as a first resistance value and outputs an ODT flag signal, in response to an ODT request from a host;
• and
• a second memory device mounted on the package substrate, and comprising second ODT resistance and a second ODT circuit, which determines a value of the second ODT resistance, wherein the second ODT circuit sets the second ODT resistance as a second resistance value, when receiving the ODT flag signal from the first memory device;
• and
• wherein the first resistance value is equal to or lower than the second resistance value, when the first ODT resistance and the second ODT resistance are connected in common to a pad receiving a command/address signal and/or a clock signal from the host.

A memory device comprising:

• a resistor circuit providing on-die-termination (ODT) resistance connected to a pad receiving a signal from an external host;
• an ODT setting circuit configured to control the resistor circuit such that the ODT resistance has a value greater than a termination resistance, when the termination resistance included in an ODT request received from the host is lower than predetermined reference resistance;
• and
• an ODT enable circuit configured to output an ODT flag signal when the termination resistance is lower than the reference resistance;
• wherein the ODT enable circuit is configured to output the ODT flag signal to a first number of the memory device, among other memory devices, when the ODT request is received together with at least one signal of a command/address signal and a clock signal, and is further configured to output the ODT flag signal to a second number of the memory device, among other memory devices, when the ODT request is received together with at least one signal of a data signal and a data strobe signal, the second number is less than the first number.