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US 11,238,920 B2Granted
Comparison operations in memory
AssigneeMicron Technology, Inc.
InventorsKyle B. Wheeler, Troy A. Manning, Richard C. Murphy
Life of this patent
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Abstract
One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
Claims20
An apparatus, comprising:
- control circuitry of a memory device configured to control sensing circuitry coupled to an array of memory cells of the memory device to:
- perform a plurality of logical operations to compare a first value to a second value,
- wherein first data representative of the first value is stored in a first portion of a number of memory cells coupled to a sense line of the array of memory cells, and
- wherein second data representative of the second value is stored in a second portion of the number of memory cells;
- and
- sequentially activate a single select line coupled to one of the number of memory cells at a time to perform at least one of the plurality of logical operations.
3 more elements
A system, comprising:
- a host device configured to generate instructions;
- and
- a memory device configured to execute instructions from the host device to:
- write, to first memory cells coupled to a sense line of an array of memory cells, first data representative of a first value;
- write, to second memory cells coupled to the sense line, second data representative of a second value;
- and
- activate, sequentially, individually, and independently, select lines coupled to the first and second memory cells to compare the first value to the second value,
- wherein the memory device comprises logical operation selection logic coupled to the first and second sense lines and configured to indicate, a plurality of logical operations to be performed to compare the first value to the second value.
5 more elements
An apparatus, comprising:
- sensing circuitry comprising respective sense amplifiers and respective compute components coupled to each of a plurality of pairs of complementary sense lines of an array of memory cells,
- wherein the sensing circuitry is configured to perform a sequence of logical operations, using the compute components, on:
- first data representative of first values stored by first memory cells of the array of memory cells;
- and
- second data representative of second values stored by second memory cells of the array of memory cells,
- wherein performance of the sequence of logical operations comprises:
- a comparison of the first values to the second values;
- and
- sequential, individual, and independent activation of select lines of the array of memory cells coupled to the first and second memory cells, and
- wherein the sensing circuitry further comprises logical operation selection logic coupled to the plurality of pairs of complementary sense lines and configured to indicate, to the compute components, each logical operation of the sequence to be performed.
7 more elements
An apparatus, comprising:
- sensing circuitry comprising respective sense amplifiers and respective compute components coupled to each of a plurality of pairs of complementary sense lines of an array of memory cells,
- wherein the sensing circuitry is configured to:
- perform a sequence of logical operations, using the compute components, on:
- first data representative of first values stored by first memory cells of the array of memory cells;
- and
- second data representative of second values stored by second memory cells of the array of memory cells;
- and
- write, to third memory cells of the array of memory cells, results of respective comparisons of the first values to the second values,
- wherein the first, second, and third memory cells are coupled to the plurality of pairs of complementary sense lines,
- wherein performance of the sequence of logical operations comprises:
- a comparison of the first values to the second values;
- and
- sequential, individual, and independent activation of select lines of the array of memory cells coupled to the first and second memory cells, and
- wherein each respective result of a comparison of comprises data indicative of one of:
- a respective first value being greater than a respective second value;
- the respective first value being less than the respective second value;
- and
- the respective first value being equal to the respective second value.
15 more elements
Dependencies are inferred from the claim text.