Memory device having low write error rate
AssigneeSamsung Electronics Co., Ltd.
InventorSang-Hoon Jung
Life of this patent
Estimating the term…
Abstract
A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.
Claims12
A memory device comprising:
- a cell array including a plurality of memory cells;
- an address register configured to receive a first address and latch the first address;
- an address transition detector configured to receive a second address and detect change of the second address from the latched first address and output, when the change of the second address from the latched first address is detected, a transition detection signal;
- and
- a control logic circuit configured to start a write operation on the cell array using the first address by a write signal and terminate the write operation in response to the transition detection signal.
Dependencies are inferred from the claim text.