Semiconductor device performing row hammer refresh operation

An apparatus comprising:

• a memory cell array including a plurality of word lines each coupled to a plurality of memory cells;
• and
• a control circuit configured to activate a first internal signal in response to a first external command,
• wherein the memory cell array is divided into first and second groups,
• wherein a first number of the plurality of word lines in the first group are selected in response to the first internal signal, and
• wherein a second number of the plurality of word lines in the second group are selected in response to the first internal signal, the second number is smaller than the first number.

An apparatus comprising:

• a memory cell array including a plurality of word lines each coupled to a plurality of memory cells;
• a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command;
• a first address storing circuit storing an address signal that is updated in response to the first internal signal;
• a second address storing circuit storing an address signal that is updated in response to an access history of the memory cell array;
• and
• a row logic circuit configured to select one or more word lines corresponding to the address signal supplied from the first address storing circuit in response to the first internal signal, and to select one or more word lines corresponding to the address signal supplied from the second address storing circuit in response to the second internal signal.