Apparatuses and methods for compute components formed over an array of memory cells
AssigneeMicron Technology, Inc.
InventorJason T. Zawodny
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.
Claims17
An apparatus, comprising:
- an array of memory cells comprising a first plurality of transistors comprising a first semiconductor material;
- and
- a compute component formed over the array of memory cells and comprising a second plurality of transistors comprising a second semiconductor material having a different concentration of doping ions than the first semiconductor material,
- wherein the second semiconductor material has a higher concentration of doping ions than the first semiconductor material.
A method, comprising:
- forming, over an array of storage elements, a plurality of transistors comprising a semiconductor material;
- doping the semiconductor material to a higher concentration of doping ions than a concentration of doping ions of another semiconductor material of the array of storage elements;
- and
- forming sensing circuitry in the semiconductor material.
A method, comprising:
- forming, over an array of storage elements, a first plurality of transistors comprising a first semiconductor material and a second plurality of transistors comprising a second semiconductor material,
- wherein the second semiconductor material has a different concentration of doping ions than the first semiconductor material corresponding to a higher leakage current of the second plurality of transistors than that of the first plurality of transistors.
An apparatus, comprising:
- an array of memory cells comprising a first plurality of transistors comprising a first semiconductor material;
- and
- a compute component formed over the array of memory cells and comprising a second plurality of transistors comprising a second semiconductor material having a different concentration of doping ions than the first semiconductor material,
- wherein the second semiconductor material has a lower concentration of doping ions than the first semiconductor material.
An apparatus, comprising:
- an array of memory cells comprising a first plurality of transistors comprising a first semiconductor material;
- and
- a compute component formed over the array of memory cells and comprising a second plurality of transistors comprising a second semiconductor material having a different concentration of doping ions than the first semiconductor material,
- wherein the different concentration of doping ions corresponds to a shorter refresh cycle of the second plurality of transistors than that of the first plurality of transistors.
A method, comprising:
- forming, over an array of storage elements, a plurality of transistors comprising a semiconductor material;
- doping the semiconductor material to a lower concentration of doping ions than a concentration of doping ions of another semiconductor material of the array of storage elements;
- and
- forming sensing circuitry in the semiconductor material.
Dependencies are inferred from the claim text.