Memory circuit and method of operating same

A memory circuit comprising:

• a word line;
• a first bit line;
• a second bit line;
• a memory array having a first memory cell and a second memory cell arranged in a first row, the first memory cell and the second memory cell being coupled to the word line;
• and
• an input output circuit comprising:
• a sense amplifier coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line, the sense amplifier being responsive to a first sense amplifier signal and a second sense amplifier signal different from the first sense amplifier signal, the sense amplifier comprising:
• a header switch having a first size and being coupled between a first node and a first supply voltage;
• and
• a footer switch having a second size and being coupled between a second node and a second supply voltage different from the first supply voltage, the first size being greater than the second size;
• wherein the first size includes a first number of fins or a first channel width;
• and
• the second size includes a second number of fins or a second channel width.

A method of operating a sense amplifier, the method comprising:

• writing data to a first memory cell and a second memory cell;
• reading the data from the first memory cell and the second memory cell, wherein reading the data comprises:
• pre-charging, by a pre-charge circuit, a first bit line and a second bit line to a pre-charge voltage level based on a first signal, the pre-charge voltage level corresponding to a first logical value, the pre-charge circuit being coupled to the first bit line and the second bit line;
• and
• turning on the sense amplifier responsive to a second signal and a third signal, the second signal and the third signal being different from each other;
• and
• outputting a set of data based on the data stored in the first memory cell and the second memory cell that are reflected on the first bit line and the second bit line, respectively.