Using embedded switches for reducing capacitive loading on a memory system

A memory array comprising:

• a first set of memory cells and a second set of memory cells, each set of memory cells extending across a plurality of layers of the memory array, each layer including a memory cell of the first set of memory cells and a memory cell of the second set of memory cells;
• a first group of switches, each including:
• a first electrode, and
• a second electrode connected to a global select line;
• a second group of switches, each including:
• a first electrode, and
• a second electrode connected to the global select line;
• a third group of switches, each including:
• a first electrode connected to the first electrode of the first group of switches, and
• a second electrode connected to first electrodes of the first subset of memory cells;
• and
• a fourth group of switches, each including:
• a first electrode connected to the first electrode of the second group of switches, and
• a second electrode connected to first electrodes of the second subset of memory cells.

A memory system comprising:

• a memory array including:
• a first group of switches;
• a first set of memory cells having first electrodes coupled to a first local select line and second electrodes coupled to the first group of switches;
• a second set of memory cells having first electrodes coupled to a second local select line and second electrodes coupled to the first group of switches;
• and
• a controller connected to the memory array, the controller is to:
• toggle at least one switch of the first group of switches to electrically couple a global bit line to the second electrodes of the first set of memory cells.