Circuit layout structure for volatile memory modules and memory storage device

A memory storage device, comprising:

• a rewritable non-volatile memory module;
• a plurality of first volatile memory modules belonging to different ranks;
• a plurality of second volatile memory modules belonging to the different ranks;
• a first data line, coupled to the first volatile memory modules without crossing any one of the first volatile memory modules and configured to access at least one of the first volatile memory modules through a first continuous bit group;
• a second data line, coupled to the second volatile memory modules without crossing any one of the second volatile memory modules and configured to access at least one of the second volatile memory modules through a second continuous bit group;
• a first clock enable signal line, coupled to the first volatile memory modules and configured to control the first volatile memory modules to enter a self-refresh mode in parallel;
• a second clock enable signal line, coupled to the second volatile memory modules and configured to control the second volatile memory modules to enter the self-refresh mode in parallel;
• and
• a memory control circuit unit, coupled to the rewritable non-volatile memory module, the first data line, the second data line, the first clock enable signal line and the second clock enable signal line.

A circuit layout structure, comprising:

• a plurality of volatile memory modules, wherein the volatile memory modules include a plurality of volatile memory modules belonging to a first rank and a plurality of volatile memory modules belonging to a second rank, and only the volatile memory modules belonging to one of the first rank and the second rank are operated at a point in time;
• a clock enable signal line, coupled to one of the volatile memory modules belonging to the first rank and one of the volatile memory modules belonging to the second rank;
• and
• a data line, coupled to the one of the volatile memory modules belonging to the first rank and the one of the volatile memory modules belonging to the second rank without crossing any one of the one of the volatile memory modules belonging to the first rank and the one of the volatile memory modules belonging to the second rank.

A memory storage device, comprising:

• a rewritable non-volatile memory module;
• a plurality of volatile memory modules, wherein the volatile memory modules include a plurality of volatile memory modules belonging to a first rank and a plurality of volatile memory modules belonging to a second rank, and only the volatile memory modules belonging to one of the first rank and the second rank are operated at a point in time;
• a clock enable signal line, coupled to one of the volatile memory modules belonging to the first rank and one of the volatile memory modules belonging to the second rank;
• a data line, coupled to the one of the volatile memory modules belonging to the first rank and the one of the volatile memory modules belonging to the second rank without crossing any one of the one of the volatile memory modules belonging to the first rank and the one of the volatile memory modules belonging to the second rank;
• and
• a memory control circuit unit, coupled to the rewritable non-volatile memory module, the volatile memory modules, the clock enable signal line and the data line.