Dual gate line drive circuit, array substrate, and display device

A gate drive circuit comprising:

• a plurality of cascaded shift registers, wherein the shift registers at respective stages output respective first signals;
• a plurality of control circuits, wherein each control circuit is coupled to a respective shift register, and is configured to process the respective first signal to generate a respective second signal, and wherein the effective voltage levels of the second signals are spaced apart in a time domain;
• a plurality of level shifters, wherein each level shifter is coupled to a respective control circuit, and is configured to convert the voltage level of the respective second signal to generate a respective third signal;
• a plurality of voltage stabilization circuits, wherein each voltage stabilization circuit is coupled to a respective level shifter, and is configured to stabilize the respective third signal, and wherein the stabilized third signal is outputted as a fourth signal;
• and
• a plurality of first exchanging circuits, wherein the first exchanging circuit is configured to enable any of the following:
• exchanging the first signals at a 2nth stage and a (2n+1)th stage, exchanging the second signals at the 2nth stage and the (2n+1)th stage, exchanging the third signals at the 2nth stage and the (2n+1)th stage, and exchanging the fourth signals at the 2nth stage and the (2n+1)th stage, wherein n is a natural number;
• wherein the first exchanging circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor,
• wherein a control electrode of the first transistor is coupled to a first control signal terminal, wherein a first electrode of the first transistor is coupled to an output terminal of the shift register at the 2nth stage, and wherein a second electrode of the first transistor is coupled to an input terminal of the control circuit at the 2nth stage;
• wherein a control electrode of the second transistor is coupled to the first control signal terminal, wherein a first electrode of the second transistor is coupled to the output terminal of the shift register at the 2nth stage, and wherein a second electrode of the second transistor is coupled to an input terminal of the control circuit at the (2n+1)th stage;
• wherein a control electrode of the third transistor is coupled to the first control signal terminal, wherein a first electrode of the third transistor is coupled to an output terminal of the shift register at the (2n+1)th stage, and wherein a second electrode of the third transistor is coupled to the input terminal of the control circuit at the 2nth stage;
• and wherein a control electrode of the fourth transistor is coupled to the first control signal terminal, wherein a first electrode of the fourth transistor is coupled to the output terminal of the shift register at the (2n+1)th stage, and wherein a second electrode of the fourth transistor is coupled to the input terminal of the control circuit at the (2n+1)th stage;
• or
• wherein a control electrode of the first transistor is coupled to a first control signal terminal, wherein a first electrode of the first transistor is coupled to an output terminal of the control circuit at the 2nth stage, and wherein a second electrode of the first transistor is coupled to an input terminal of the level shifter at the 2nth stage;
• wherein a control electrode of the second transistor is coupled to the first control signal terminal, wherein a first electrode of the second transistor is coupled to the output terminal of the control circuit at the 2nth stage, and wherein a second electrode of the second transistor is coupled to an input terminal of the level shifter at the (2n+1)th stage;
• wherein a control electrode of the third transistor is coupled to the first control signal terminal, wherein a first electrode of the third transistor is coupled to an output terminal of the control circuit at the (2n+1)th stage, and wherein a second electrode of the third transistor is coupled to the input terminal of the level shifter at the 2nth stage;
• and wherein a control electrode of the fourth transistor is coupled to the first control signal terminal, wherein a first electrode of the fourth transistor is coupled to the output terminal of the control circuit at the (2n+1)th stage, and wherein a second electrode of the fourth transistor is coupled to the input terminal of the level shifter at the (2n+1)th stage;
• or
• wherein a control electrode of the first transistor is coupled to a first control signal terminal, wherein a first electrode of the first transistor is coupled to an output terminal of the level shifter at the 2nth stage, and wherein a second electrode of the first transistor is coupled to an input terminal of the voltage stabilization circuit at the 2nth stage;
• wherein a control electrode of the second transistor is coupled to the first control signal terminal, wherein a first electrode of the second transistor is coupled to the output terminal of the level shifter at the 2nth stage, and wherein a second electrode of the second transistor is coupled to an input terminal of the voltage stabilization circuit at the (2n+1)th stage;
• wherein a control electrode of the third transistor is coupled to the first control signal terminal, wherein a first electrode of the third transistor is coupled to an output terminal of the level shifter at the (2n+1)th stage, and wherein a second electrode of the third transistor is coupled to the input terminal of the voltage stabilization circuit at the 2nth stage;
• and wherein a control electrode of the fourth transistor is coupled to the first control signal terminal, wherein a first electrode of the fourth transistor is coupled to the output terminal of the level shifter at the (2n+1)th stage, and wherein a second electrode of the fourth transistor is coupled to the input terminal of the voltage stabilization circuit at the (2n+1)th stage;
• or
• wherein a control electrode of the first transistor is coupled to a first control signal terminal, wherein a first electrode of the first transistor is coupled to an output terminal of the voltage stabilization circuit at the 2nth stage, and wherein a second electrode of the first transistor is coupled to a 2nth output terminal of the gate drive circuit wherein a control electrode of the second transistor is coupled to the first control signal terminal, wherein a first electrode of the second transistor is coupled to the output terminal of the voltage stabilization circuit at the 2nth stage, and wherein a second electrode of the second transistor is coupled to a (2n+1)th output terminal of the gate drive circuit wherein a control electrode of the third transistor is coupled to the first control signal terminal, wherein a first electrode of the third transistor is coupled to an output terminal of the voltage stabilization circuit at the (2n+1)th stage, and wherein a second electrode of the third transistor is coupled to the 2nth output terminal of the gate drive circuit and wherein a control electrode of the fourth transistor is coupled to the first control signal terminal, wherein a first electrode of the fourth transistor is coupled to the output terminal of the voltage stabilization circuit at the (2n+1)th stage, and wherein a second electrode of the fourth transistor is coupled to the (2n+1)th output terminal of the gate drive circuit.