Stage with multiple output buffers and scan driver having the same

A stage that outputs a scan signal and a sensing signal to a scan line and a sensing line, respectively, the stage comprising:

• a first controller configured to control a voltage of a sensing node and a voltage of a driving node based on a first control signal, a second control signal, a third control signal, a carry signal of the stage, and a carry signal of another stage connected to the stage;
• a second controller configured to control a voltage of an inversion driving node based on a first carry clock signal, the voltage of the driving node, and the third control signal;
• a first output buffer configured to output a second carry clock signal or a second low potential power as the carry signal in correspondence with the voltage of the driving node and the voltage of the inversion driving node;
• a second output buffer configured to output a scan clock signal or a first low potential power as the scan signal in correspondence with the voltage of the driving node and the inversion driving node;
• and
• a third output buffer configured to output a sensing clock signal or the first low potential power as the sensing signal in correspondence with the voltage of the driving node and the voltage of the inversion driving node,
• wherein the first controller comprises:
• a first transistor connected between a first input terminal receiving a scan start signal or a carry signal of a previous stage connected to the stage and the driving node, and having a gate electrode connected to the first input terminal;
• a second transistor and a third transistor connected in series between a third power input terminal receiving high potential power and the driving node, and having gate electrodes connected to the sensing node and a second control signal input terminal receiving the second control signal, respectively;
• a fourth transistor connected between the second power input terminal receiving the first low potential power and the driving node, and having a gate electrode connected to a third control signal input terminal receiving the third control signal;
• a sixth transistor connected between a first output terminal outputting the carry signal and the sensing node, and having a gate electrode connected to a first control signal input terminal receiving the first control signal;
• an eighth transistor connected between the driving node and a second power input terminal receiving the second low potential power, and having a gate electrode receiving a carry signal of a next stage connected to the stage;
• and
• a first capacitor connected between the third power input terminal and the sensing node.

A stage that outputs a scan signal and a sensing signal to a scan line and a sensing line, respectively, the stage comprising:

• a first controller configured to control a voltage of a sensing node and a voltage of a driving node based on a first control signal, a second control signal, a third control signal, a carry signal of the stage, and a carry signal of another stage connected to the stage;
• a second controller configured to control a voltage of an inversion driving node based on a first carry clock signal, the voltage of the driving node, and the third control signal;
• a first output buffer configured to output a second carry clock signal or a second low potential power as the carry signal in correspondence with the voltage of the driving node and the voltage of the inversion driving node;
• a second output buffer configured to output a scan clock signal or a first low potential power as the scan signal in correspondence with the voltage of the driving node and the inversion driving node;
• a third output buffer configured to output a sensing clock signal or the first low potential power as the sensing signal in correspondence with the voltage of the driving node and the voltage of the inversion driving node;
• and
• a third controller configured to transfer the second low potential power to the driving node when the second carry clock signal is input while the inversion driving node is set to a gate on voltage.