Shift register unit using clock signals, gate drive circuit, display panel, display device and driving method

A shift register unit, comprising a first sub-unit and a leakage prevention circuit, and the first sub-unit comprises a first input circuit, a first output circuit, a blanking input sub-unit and a second sub-unit, wherein

• the first input circuit is configured to control a level of a first node in response to a first input signal,
• the first output circuit is configured to provide an output signal at an output terminal under control of the level of the first node, and
• the leakage prevention circuit is connected to the first node and a first voltage terminal, and is configured to control a level of a leakage prevention node under control of the level of the first node, so as to form a conductive path between the leakage prevention node and the first voltage terminal and turn off a circuit connected between the first node and the leakage prevention node,
• wherein the leakage prevention circuit comprises a first leakage prevention sub-circuit and a second leakage prevention sub-circuit,
• the first leakage prevention sub-circuit is connected to the first node and the leakage prevention node, and is configured to control the level of the leakage prevention node under control of the level of the first node, and
• the second leakage prevention sub-circuit is connected to the leakage prevention node and the first voltage terminal, and the second leakage prevention sub-circuit is configured to form the conductive path between the leakage prevention node and the first voltage terminal under control of the level of the leakage prevention node or the level of the first node,
• the blanking input sub-unit is connected to the first node, and is configured to receive a selection control signal and control the level of the first node;
• the second sub-unit comprises a second input circuit and a second output circuit, the second input circuit is configured to control a level of a second node in response to the first input signal, and the second output circuit is configured to output a second output signal under control of the level of the second node, and wherein
• the second output signal of the second output circuit and the first output signal of the first output circuit correspond to a same stage of the shift register unit, and the second output signal of the second output circuit is used for compensating a row of sub-pixel units during a blanking period of one frame.