Shift register unit, driving method, gate driving circuit and display device

A shift register unit, comprising an input sub-circuitry, a pull-up node control sub-circuitry, a pull-down node control sub-circuitry, a gate driving output sub-circuitry, and a carry signal output sub-circuitry,

• wherein the input sub-circuitry is coupled to an input end, a second clock signal input end and a pull-up node, and configured to write an input signal from the input end into the pull-up node at an input stage under the control of the second clock signal input end;
• the pull-up node control sub-circuitry is coupled to the pull-up node, a pull-down node, a first clock signal input end and a first voltage input end, and configured to write a first voltage into the pull-up node at a restoration stage under the control of the first clock signal input end and the pull-down node;
• the first voltage input end is configured to input the first voltage;
• the pull-down node control sub-circuitry is coupled to the pull-down node, the pull-up node, the first clock signal input end, the first voltage input end and a second voltage input end, and configured to write the first voltage into the pull-down node at the input stage and an output stage under the control of the pull-up node, and write a second voltage into the pull-down node at the restoration stage under the control of the first clock signal input end;
• the second voltage input end is configured to input the second voltage;
• the gate driving output sub-circuitry is coupled to the pull-up node, the pull-down node, a gate driving signal output end, a third clock signal input end and a third voltage input end, and configured to output a third clock signal via the gate driving signal output end at the input stage and the output stage under the control of the pull-up node, and output a third voltage via the gate driving signal output end at the restoration stage under the control of the pull-down node;
• the third clock signal input end is configured to input the third clock signal, and the third voltage input end is configured to input the third voltage;
• and
• the carry signal output sub-circuitry is coupled to the pull-up node, the pull-down node, a carry signal output end, the third clock signal input end and the third voltage input end, and configured to control a potential at the pull-up node, output the third clock signal via the carry signal output end at the input stage and the output stage under the control of the pull-up node, and output the third voltage via the carry signal output end at the restoration stage under the control of the pull-down node.