Method and system for fabricating integrated circuit with aid of programmable circuit synthesis

A method for fabricating an integrated circuit, comprising:

• assigning a set of parameter values to a set of size parameters of a unit cell of the integrated circuit in a unit cell schematic of the unit cell by referring to an intrinsic gain of at least one transistor of unit cell, wherein the intrinsic gain of the at least one transistor of the unit cell, characterized by the set of parameter values, is set to a gain value falling within a predetermined range;
• generating a unit cell layout of the unit cell according to the unit cell schematic;
• generating a circuit layout comprising a plurality of replicas of the unit cell layout, the replicas of the unit cell layout being arranged in correspondence with circuit blocks in a circuit floorplan of the integrated circuit, respectively;
• and
• fabricating the integrated circuit according to the circuit layout.

A system for fabricating an integrated circuit, comprising:

• a control circuit;
• a storage device, coupled to the control circuit, the storage device being configured to store a circuit design database and a program code, wherein the circuit design database stores a plurality of circuit characteristics corresponding to a unit cell of the integrated circuit, and a plurality of candidate sets of parameter values for a set of size parameters of the unit cell are used to characterize the unit cell to obtain the circuit characteristics, respectively;
• when executed by the control circuit, the program code causes the control circuit to:
• create a first cell schematic of the unit cell, the set of size parameters of the unit cell being assigned a set of parameter values, the unit cell in the first cell schematic characterized by the set of parameter values;
• create a second cell schematic of the unit cell according to the circuit design database by revising the set of parameter values of the unit cell in the first cell schematic according to an intrinsic gain of at least one transistor of the unit cell, wherein the set of size parameters of the unit cell in the second cell schematic has one of the candidate set of parameter values, the intrinsic gain of the at least one transistor of the unit cell characterized by the set of parameter values is set to a gain value falling within a predetermined range;
• generate a cell layout of the unit cell according to the second cell schematic;
• and
• fabricate the integrated circuit according to the cell layout of the unit cell.