Transmitter test with interpolation

A method comprising:

• for each individual interpolator phase position in a plurality of interpolator phase positions supported by a phase interpolator:
• generating, by the phase interpolator, an interpolated clock signal based on a set of clock signals while the phase interpolator is set to the individual interpolator phase position;
• generating, by a digital data generator, a pre-determined data pattern;
• generating, by a serializer, serialized digital data based on the pre-determined data pattern, where the serializer operates based on the set of clock signals;
• sampling, by a data sampler operating based on the interpolated clock signal, the serialized digital data;
• collecting, by a pattern checker operating based on the interpolated clock signal, a plurality of sampled bits for the individual phase interpolator as the digital data generator generates the pre-determined data pattern, the plurality of sampled bits being provided by the data sampler;
• error checking, by the pattern checker, the plurality of sampled bits for the individual interpolator phase position based on the pre-determined data pattern;
• generating, by the pattern checker, an error check result for the individual interpolator phase position based on the error checking the plurality of sampled bits;
• and
• adding, by a test controller, the error check result to a plurality of error check results;
• and
• generating, by the test controller, a test result for a data transmission test based on the plurality of error check results.

A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors of a computing device, cause the computing device to generate a circuit design by performing operations comprising:

• configuring, in the circuit design, a digital data generator that comprises a parallel data output, the parallel data output providing parallel digital data, the parallel digital data being generated by the digital data generator;
• configuring, in the circuit design, a serializer coupled to the parallel data output, the serializer comprising a serial data output, the serial data output providing serialized digital data, the serialized digital data being generated by the serializer based on the parallel digital data and a set of clock signals;
• configuring, in the circuit design, a phase interpolator that comprises a phase interpolator clock output, the phase interpolator clock output providing an interpolated clock signal, the interpolated clock signal being generated by the phase interpolator based on the set of clock signals;
• configuring, in the circuit design, a data sampler coupled to the serial data output and the phase interpolator clock output, the data sampler comprising a data sampler output, and the data sampler being configured to sample the serialized digital data based on the interpolated clock signal;
• configuring, in the circuit design, a pattern checker coupled to the data sampler output and the phase interpolator clock output;
• and
• configuring, in the circuit design, a test controller configured to perform a data transmission test by:
• receiving, from the pattern checker, a plurality of error check results for a plurality of interpolator phase positions supported by the phase interpolator, the plurality of error check results being generated based on a plurality of sampled bits collected by the pattern checker, from the data sampler, as the digital data generator generates a pre-determined data pattern;
• and
• generating a test result for the data transmission test based on the plurality of error check results.