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US 11,238,202 B2Granted
Verifying glitches in reset path using formal verification and simulation
AssigneeSynopsys, Inc.
InventorsSudeep Mondal, Paras Mal Jain, Anshul Tuteja
Life of this patent
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Abstract
A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the sub-circuit, and performing a simulation or a formal verification of the optimized HDL output file to determine whether a signal associated with the net glitches.
Claims19
A method, comprising:
- identifying a sub-circuit that drives a net from a plurality of nets in a circuit;
- generating previous cycle variables for a plurality of inputs of the sub-circuit
- generating, by a computer processor, a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit and configured to detect a glitch type by generating a glitch modeling output as a function of at least a value of the net and a previous value of the net, wherein generating the glitch detection circuit further comprises:
- generating a high rail net value of the glitch detection circuit based on the plurality of inputs to the sub-circuit, and
- generating a low rail net value of the glitch detection circuit based on the previous cycle variables;
- modifying the sub-circuit to include the glitch detection circuit having the low rail net value and the high rail net value;
- generating a hardware design language (HDL) output file associated with a resynthesized netlist of the modified sub-circuit;
- and
- performing a simulation or a formal verification, of the HDL output file to determine whether a signal associated with the net glitches.
6 more elements
A system comprising:
- a memory storing instructions;
- and
- a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- identify a sub-circuit that drives a net from a plurality of nets in a circuit,
- generate previous cycle variables for a plurality of inputs of the sub-circuit,
- generate a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit and configured to detect a glitch type by generating a glitch modeling output as a function of at least a value of the net and a previous value of the net,
- generate a high rail net value of the glitch detection circuit based on the plurality of inputs to the sub-circuit,
- generate a low rail net value of the glitch detection circuit based on the previous cycle variables,
- modify the sub-circuit to include the glitch detection circuit having the low rail net value and the high rail net value,
- generate a hardware design language (HDL) output file associated with a resynthesized netlist of the modified sub-circuit, and
- perform a simulation or a formal verification of the HDL output file to determine whether a signal associated with the net glitches.
8 more elements
A method, comprising:
- identifying a sub-circuit that drives a net from a plurality of nets in a circuit;
- generating an abstract port for a signal driver of the sub-circuit when the signal driver is associated with a primary port of the circuit;
- generating previous cycle variables for a plurality of inputs of the sub-circuit;
- generating, by a computer processor, a glitch detection circuit comprising dual-rail encoding from the net to the signal driver of the sub-circuit and is configured to detect a glitch type by generating a glitch modeling output as a function of at least a value of the net and a previous value of the net, wherein generating the glitch detection circuit further comprises:
- generating a high rail net value of the glitch detection circuit based on the plurality of inputs to the sub-circuit, and
- generating a low rail net value of the glitch detection circuit based on the previous cycle variables;
- modifying the sub-circuit to include the glitch detection circuit having the low rail net value and the high rail net value;
- and
- performing one of a simulation and a formal verification of the output file to determine whether a signal associated with the net glitches.
6 more elements
Dependencies are inferred from the claim text.