Interface clock management
AssigneeRambus Inc.
InventorYuanlong Wang
Life of this patent
Estimating the term…
Abstract
The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
Claims20
A controller, comprising:
- a first driver circuit to selectively transmit a clock signal to a plurality of memory devices;
- an interface to transmit a command to the plurality of memory devices, timed by the clock signal, that specifies an access of data;
- and,
- a first receiver circuit to receive, collectively from the plurality of memory devices, a first indicator indicating the plurality of memory devices are collectively ready to not receive the clock signal, the first receiver circuit to receive, from at least a first memory device of the plurality of memory devices, a second indicator indicating the first memory device is ready to receive the clock signal to time a data transfer.
A controller, comprising:
- a first driver circuit to selectively transmit a clock signal to a plurality of memory devices;
- an interface to transmit a command to the plurality of memory devices timed by the clock signal;
- a first receiver circuit to receive, collectively from the plurality of memory devices, a first indicator indicating the plurality of memory devices are collectively ready to not receive the clock signal, the first receiver circuit to receive, from at least a first memory device of the plurality of memory devices a second indicator indicating the first memory device is ready to receive the clock signal to time a data transfer;
- and,
- a plurality of receivers to receive a data transfer based on the clock signal.
A first memory device, comprising:
- a first receiver circuit to receive a selectively transmitted clock signal;
- an interface to receive a command, from a controller and timed by the clock signal, that specifies an access of data;
- and,
- a first driver circuit to, collectively with a second memory device, transmit a first indicator to a controller, the first indicator indicating to the controller that the first memory device and the second memory device are collectively ready to not receive the clock signal, the first driver circuit to transmit a second indicator indicating to the controller that at least the first memory device is ready to receive the clock signal to time a data transfer.
Dependencies are inferred from the claim text.