Operation cache compression
AssigneeArm Limited
InventorsMichael Brian Schinzler, Michael Filippo
Life of this patent
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Abstract
A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.
Claims12
A data processing method comprising:
- fetching instructions from storage circuitry;
- decoding each of the instructions into one or more operations, wherein the decoding decodes at least one of the instructions into a plurality of operations;
- providing the one or more operations to one or more execution units;
- and
- caching the one or more operations in cache circuitry,
- wherein at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations, wherein
- for each of a plurality of lanes, the compressed entry is expanded into one of the plurality of operations as indicated by an associated lookup table of that lane based on the compressed entry and the one of the plurality of operations is provided to one of the one or more execution units via that lane;
- and
- contents of the associated lookup table differs for at least some of the plurality of lanes for the compressed entry.
A data processing apparatus comprising:
- fetch circuitry to fetch instructions from storage circuitry;
- decode circuitry to decode each of the instructions into one or more operations and to provide the one or more operations to one or more execution units, wherein the decode circuitry is adapted to decode at least one of the instructions into a plurality of operations;
- and
- cache circuitry to cache the one or more operations, wherein
- at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations;
- a plurality of lanes, each having an associated expansion circuit and an associated lookup table, wherein for each lane, the associated expansion circuit is configured to expand the compressed entry into one of the plurality of operations as indicated by the associated lookup table based on the compressed entry and provide the one of the plurality of operations to one of the one or more execution units via that lane;
- and
- contents of the associated lookup table differs for at least some of the plurality of lanes for the compressed entry.
Dependencies are inferred from the claim text.