Reduce data traffic between cache and memory via data access of variable sizes
AssigneeMicron Technology, Inc.
InventorSteven Jeffrey Wallach
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorSteven Jeffrey Wallach
Estimating the term…
A computing system, method and apparatus to cache a portion of a data block. A processor can access data using memory addresses in an address space. A first memory can store a block of data at a block of contiguous addresses in the space of memory address. A second memory can cache a first portion of the block of data identified by an item selection vector. For example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. Thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.
A computing device, comprising:
A method, comprising:
A non-transitory computer storage medium storing instructions which when executed in a computing system, cause the computing system to perform a method, the method comprising:
Dependencies are inferred from the claim text.