System and method for event monitoring in cache coherence protocols without explicit invalidations

A computer system comprising:

• multiple processor cores;
• at least one local cache memory associated with and operatively coupled to each core for storing one or more cache lines accessible only by the associated core;
• a shared memory, the shared memory being operatively coupled to the local cache memories and accessible by the cores, the shared memory being capable of storing a plurality of cache lines;
• and
• wherein a core issuing a callback-read to a memory address reads a last value written in the memory address when a callback marker corresponds to a first value for the memory address, and the core issuing the callback-read to the memory address is blocked from reading the memory address when the callback marker corresponds to a second value for the memory address until a next write takes place in the memory address and then reads a new value of said next write, such that the callback-read enables event monitoring for coherence of the at least one local cache and the shared memory without using explicit invalidations.