Method and apparatus for asynchronous memory write-back in a data processing system
AssigneeArm Limited
InventorsCurtis Glenn Dunham, Pavel Shamis
Life of this patent
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Abstract
A data processing system includes a processor, a memory system, a cache controller and a cache accessible by the processor via the cache controller. The cache controller provides an asynchronous interface between the processor and the memory system. Instructions, issued by the processor to the cache controller, are completed by the cache controller without blocking the processor. In addition, the cache controller tracks a completion status of the memory operation associated with each instruction and enables the completion status to be queried by the processor. Status of the memory operation may be recorded as an entry in a log, where the log, or a property of the log, is accessible by the processor.
Claims16
A method of operation of a data processing system, the method comprising:
- receiving, from a processor of the data processing system at a cache controller of the data processing system, a first instruction to perform a first memory operation;
- indicating, by the cache controller, completion of the first instruction to the processor;
- initiating the first memory operation in the cache controller, including:
- writing a new entry for the first memory operation in an operation queue;
- storing metadata for the new entry;
- and
- recording an entry in a log, the entry indicating a status of the first memory operation, where the log, or a property of the log, is accessible by the processor;
- accessing an entry of the operation queue for an uninitiated second memory operation;
- initiating the second memory operation in a memory system via a memory interface in accordance with accessed entry;
- updating the metadata for the entry to indicate that the second memory operation has been initiated;
- providing, by the memory system to the cache controller, notification of completion of the second memory operation;
- responsive to receiving the notification of completion of the second memory operation:
- updating the entry in the log indicating the status of the second memory operation;
- updating metadata for the completed second memory operation to indicate that the second memory operation has been completed;
- and
- marking the entry in the operation queue, corresponding to the completed second memory operation, as non-valid.
A data processing system comprising:
- a processor;
- a memory system;
- a cache controller configured to provide an asynchronous interface between the processor and the memory system;
- and
- a cache accessible by the processor via the cache controller,
- where one or more first instructions, issued by the processor to the cache controller, for one or more first memory operations, are completed by the cache controller without blocking the processor,
- where the memory system is configured to send a notification of completion for a memory operation initiated by the cache controller, and
- where the cache controller is configured to track a completion status of memory operations of the one or more first memory operations, including:
- responsive to receiving a first instruction, from the processor, to perform a first memory operation:
- indicate completion of the first instruction to the processor,
- write a new entry for the first memory operation in an operation queue,
- store metadata for the new entry, and
- record an entry in a log, the entry indicating a status of the first memory operation, where the log, or a property of the log, is accessible by the processor,
- access an entry of the operation queue for an uninitiated second memory operation,
- initiate the second memory operation in the memory system in accordance with accessed entry,
- update metadata for the entry to indicate that the second memory operation has been initiated,
- receive, from the memory system, notification of completion of the second memory operation,
- responsive to receiving the notification of completion of the second memory operation:
- update the entry in the log indicating the status of the second memory operation,
- update metadata for the completed second memory operation to indicate that the second memory operation has been completed, and
- mark the entry in the operation queue, corresponding to the completed second memory operation, as non-valid.
Dependencies are inferred from the claim text.