Memory device, method of operating memory device, and computer system including memory device

A memory device comprising:

• a cell region including a first metal pad and a plurality of memory planes;
• and
• a peripheral circuit region including a second metal pad, circuits to drive the plurality of memory planes and a controller to control the memory device, wherein:
• the plurality of memory planes provide a first memory area including first memory cells, another memory area including memory cells, and a security area, and
• the controller is configured to:
• read data stored in the first memory area using a first read operation;
• read data stored in the other memory area using a second read operation different from the first read operation;
• selectively store data in one of the first memory area and the other memory area based on a frequency of use (FOU) of the data and an importance weighting of the data;
• and
• store data having a FOU lower than a predetermined reference value and a weight higher than a predetermined threshold value in the security area, each of the first memory cells stores 1-bit data, and
• each of the memory cells stores 2 or more bits data.

A computer system comprising:

• a memory device;
• and
• a processor configured to control execution of a first operation at a first speed, control execution of a second operation at a second speed different from the first speed, and provide data to the memory device, wherein:
• the memory device comprises:
• a memory chip including a first metal pad, a first memory area including memory cells operated as single level memory cells (SLC) and included in a memory chip, a second memory area including memory cells operated as at least one of multi-level memory cells (MLC), triple level memory cells (TLC) and quad level memory cells (QLC);
• and
• a peripheral circuit chip including a second metal pad and a controller to control the memory device and vertically connected to the memory chip by the first metal pad and the second metal pad,
• the controller is configured to:
• read data stored in the first memory area using a first read operation in response to execution of the first operation;
• read data stored in the second memory area using a second read operation different from the first read operation in response to execution of the second operation;
• and
• store the data provided by the processor in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data, and
• the first read operation is a voltage sensing operation and the second read operation is a current sensing operation.