Load exploitation and improved pipelineability of hardware instructions

A computer program product comprising:

• a non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors, the program instructions when executed by the one or more processors cause the processor to:
• perform a hardware reduction instruction using an input to calculate at least one range reduction factor of the input;
• perform a hardware restoration instruction using the input to calculate at least one range restoration factor of the input;
• and
• perform a final fused multiply add (FMA) type of hardware instruction or a floating-point multiply (FM) hardware instruction by combining a value reduced by the at least one range reduction factor with the at least one range restoration factor.