Generating a balanced codeword protected by an error correction code
AssigneeMicron Technology, Inc.
InventorChristophe Vincent Antoine Laurent
Life of this patent
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Abstract
Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.
Claims26
A method, comprising:
- generating a codeword of bits comprising data bits, placeholder bits, and parity bits, wherein the bits of the codeword are mapped to packets;
- inverting one or more packets of the codeword to modify a ratio of logic values associated with the codeword, wherein a validity of the codeword is maintained after inverting the one or more packets;
- storing a portion of the codeword in a set of memory cells, the portion of the codeword comprising the data bits and the parity bits and excluding the placeholder bits;
- decoding the codeword based at least in part on the parity bits stored in the set of memory cells, the data bits stored in the set of memory cells, and a set of bits in place of the placeholder bits, wherein each bit of the set of bits is associated with a respective packet of the packets;
- and
- inverting the one or more packets based at least in part on an error in the set of bits detected by decoding the codeword.
A method, comprising:
- constructing a codeword of bits comprising data bits, placeholder bits, and parity bits;
- inverting a plurality of the bits of the codeword to modify a ratio of logic values associated with the codeword;
- storing the data bits and the parity bits in a set of memory cells after inverting the plurality of the bits;
- performing a decoding process on the stored data bits, the stored parity bits, and a set of bits that represent the placeholder bits;
- and
- inverting the plurality of the bits that were inverted based at least in part on the decoding process detecting an error in the set of bits.
A method, comprising:
- inverting a plurality of bits of a codeword that comprises data bits, placeholder bits, and parity bits;
- storing the codeword, excluding the placeholder bits, in memory after inverting the plurality of bits;
- performing a decoding process on the stored data bits, the stored parity bits, and a set of bits in place of the placeholder bits;
- and
- inverting the plurality of bits of the codeword based at least in part on an error detected in the set of bits during the decoding process.
A method, comprising:
- generating a codeword of bits comprising data bits, placeholder bits, and parity bits, wherein the bits of the codeword are mapped to packets;
- inverting one or more packets of the codeword to modify a ratio of logic values associated with the codeword, wherein each packet of the codeword comprises a respective placeholder bit mapped to that packet;
- storing the data bits, the parity bits, and a portion of the placeholder bits in a memory;
- reconstructing the codeword based at least in part on the stored data bits, the stored parity bits, and the stored portion of the placeholder bits;
- and
- inverting the one or more packets based at least in part on a logic value of the placeholder bit mapped that packet.
Dependencies are inferred from the claim text.