Pipelined read-modify-write operations in cache memory

A processor system comprising:

• a processor core configured to generate memory write requests;
• a cache memory;
• a memory controller having a holding buffer, and having a memory pipeline for processing the memory write requests to write data payloads of respective memory write requests to the cache memory, the memory pipeline including:
• an anchor stage configured to determine whether a first write request corresponds to a partial write, and if so, to write the data payload of the first write request to the holding buffer and read a set of conforming data from an address in the cache memory targeted by the first write request;
• and
• a read-modify-write (RMW) pipeline configured to operate on the first write request when the first write request corresponds to the partial write, the RMW pipeline including:
• a merge stage configured to read the data payload from the holding buffer, and to merge the set of conforming data with the data payload such that the data payload is retained to form merged data;
• and
• a syndrome generation stage configured to generate an error correction code (ECC) syndrome in response to the merged data;
• wherein the memory controller is configured to write the data payload and the ECC syndrome to the cache memory.