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US 11,237,901 B2Granted
Error correction using hierarchical decoders
AssigneeMicron Technology, Inc.
InventorsPaolo Amato, Marco Sforzin
Life of this patent
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Abstract
Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
Claims20
A memory device, comprising:
- an array;
- a first fast decoding (FD) decoder configured to:
- perform a first plurality of operations associated with a first error detection on input data retrieved from the array;
- and
- provide, based on processing the input data, a first output data, a validation flag, and a plurality of parity bits to an accurate decoding (AD) decoder;
- the AD decoder configured to:
- perform a second plurality of operations associated with a second error detection on the first output data received from the first decoder;
- provide, based on processing the first output data, a second output data and the plurality of parity bits to a second FD decoder;
- the second FD decoder configured to:
- perform a third plurality of operations associated with a third error correction on the second output data received from the AD decoder;
- and
- provide a third output data.
9 more elements
A controller coupled to a memory device, comprising:
- an accurate decoding (AD) decoder configured to:
- receive data, a validity flag, and parity bits from a first fast decoding (FD) decoder hosted by the memory device;
- responsive to determining that the validity flag is a first value, provide the data to a requesting apparatus;
- responsive to determining that the validity flag is a second value provide the data as corrected using a first plurality of error correction operations and the parity bits to a second FD decoder;
- and
- the second FD decoder configured to perform a second plurality of error correction operations on the data using the parity bits.
3 more elements
An apparatus, comprising:
- a memory array, configured to store data and parity bits;
- and
- a first fast decoding (FD) decoder configured to:
- receive the data and the parity bits;
- perform a first plurality of error correction operations on the data using the parity bits to generate corrected data;
- an accurate decoder (AD) configured to:
- receive the corrected data;
- determine whether the corrected data comprises further errors;
- responsive to determining that the corrected data comprises the further errors, request the parity bits from the memory array;
- and
- perform a second plurality of error correction operations on the corrected data using the requested parity bits to generate different corrected data;
- responsive to performing the second plurality of error correction operations, provide the different corrected data to a second FD decoder to perform additional error correction operations on the different corrected data.
9 more elements
Dependencies are inferred from the claim text.