US 11,237,827 B2 · Arithemetic logic unit register sequencing

Abstract

A graphics processing unit (GPU) sequences provision of operands to a set of operand registers, thereby allowing the GPU to share at least one of the operand registers between processing. The GPU includes a plurality of arithmetic logic units (ALUs) with at least one of the ALUs configured to perform double precision operations. The GPU further includes a set of operand registers configured to store single precision operands. For a plurality of executing threads that request double precision operations, the GPU stores the corresponding operands at the operand registers. Over a plurality of execution cycles, the GPU sequences transfer of operands from the set of operand registers to a designated double precision operand register. During each execution cycle, the double-precision ALU executes a double precision operation using the operand stored at the double precision operand register.

Claims20

Dependent claims

A method comprising:

receiving, for a plurality of threads executing at a processing unit, a plurality of operands for processing at a first arithmetic logic unit (ALU);
storing the plurality of operands at a plurality of registers sized to store single precision operands;
and
sequencing, over a plurality of execution cycles, provision of the plurality of operands from the plurality of registers to a first operand register sized to store double precision operands for processing at the ALU.

1 more element

Dependencies are inferred from the claim text.

Arithemetic logic unit register sequencing

Life of this patent

Arithemetic logic unit register sequencing

Life of this patent

Abstract

Claims20