Storage device and memory controller

A storage device comprising:

• a nonvolatile memory including a plurality of storage blocks, each of the plurality of storage blocks including a shift register;
• a write buffer that stores write target data to be written in the nonvolatile memory;
• and
• a control circuit configured to control writing and reading of data to and from the nonvolatile memory, wherein
• each of the plurality of storage blocks includes a first-in, first-out shift register, and
• the control circuit is configured to:
• read target data from a first storage block of the plurality of storage blocks;
• write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block;
• and
• when executing read processing to read read target data from any one of the plurality of storage blocks, write, in parallel with the read processing, the write target data of the write buffer in the any one of the storage blocks from which the read target data is read.

A memory controller controlling writing and reading of data to and from a nonvolatile memory including a plurality of storage blocks, each including a shift register, the memory controller comprising:

• a processing circuit configured to:
• manage a block pointer indicating a storage block as a next write destination among the plurality of storage blocks;
• update an address conversion table in which a correspondence between a logical address and a physical address is registered for each data stored in each of the plurality of storage blocks;
• read target data from a first storage block of the plurality of storage blocks;
• write the target data read from the first storage block to a storage block indicated by the block pointer among the plurality of storage blocks;
• and
• change a physical address of the target data registered in the address conversion table to a physical address of the storage block indicated by the block pointer.

A memory controller controlling writing and reading of data to and from a nonvolatile memory including a plurality of storage blocks, each including a shift register, wherein

• each of the plurality of storage blocks includes a first-in, first-out shift register, and
• the memory controller comprises a processing circuit configured to:
• write, in a write buffer, write target data to be written in the nonvolatile memory;
• read target data from a first storage block of the plurality of storage blocks;
• write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block;
• and
• when executing read processing to read read target data from any one of the plurality of storage blocks, write, in parallel with the read processing, the write target data of the write buffer in the any one of the storage blocks from which the read target data is read.

A memory controller controlling writing and reading of data to and from a nonvolatile memory including a plurality of storage blocks, each including a shift register, the memory controller comprising:

• a processing circuit configured to:
• read target data with parity from a first storage block of the plurality of storage blocks;
• cause an error correction circuit to perform error correction processing, by using the parity, on the target data read from the first storage block;
• cause the error correction circuit to generate new parity for the target data on which the error correction processing is performed;
• and
• write the target data with the new parity in a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block.