Apparatus and method of wear leveling for storage class memory using address cache

An apparatus for wear leveling control for storage class memory, the apparatus comprising:

• a cache memory;
• a storage class memory (SCM) controller coupled to the cache memory and a nonvolatile memory;
• and one or more processors;
• wherein the cache memory, the SCM controller and said one or more processors are configured to perform at least the following:
• determining whether current data to be written to a nonvolatile memory corresponds to an address cache hit or an address cache miss by comparing a destined address for the current data to be written to the nonvolatile memory and recently write addresses in the address cache, wherein the address cache only stores address part of the current data without storing data part of the current data, the address cache hit indicates that the destined address is in the address cache and the address cache miss indicates that the destined address is not in the address cache, and wherein when the address cache hit occurs, the address cache provides a logging address instead of stored data, and the logging address points to a temporary memory space in the nonvolatile memory;
• writing the current data conditionally to the destined address or a designated location in the nonvolatile memory different from the destined address depending on whether the current data corresponds to the address cache hit or the address cache miss in order to reduce repetitive write to a same destined address, wherein the designated location and destined location indicated by the destined address are able to store data;
• and wherein the current data is written to the designated location in the nonvolatile memory when the current data corresponds to the address cache hit, and the current data is written to the destined location in the nonvolatile memory when the current data corresponds to the address cache miss.

A method of damage recovery for storage class memory based on nonvolatile memory, the method comprising:

• using an address cache to store addresses of recent data write and timestamp associated with recent input data, wherein an address cache hit indicates that an address of a current data to be written to the nonvolatile memory is in the address cache and an address cache miss indicates that the address of the current data to be written to the nonvolatile memory is not in the address cache;
• dividing the nonvolatile memory into memory groups;
• mapping N input group addresses corresponding to a logic addresses of the memory groups to M output group addresses corresponding to physical group addresses of the memory groups using fixed mapping within a period T, wherein T is a positive value, M and N are positive integers and M is greater than N, wherein N memory groups are used as data groups, one or more memory groups are used as redundant groups and the redundant groups comprise one or more logging groups, M is equal to a sum of N and a number of the redundant groups, and wherein said mapping N input group addresses to M output group addresses causes N data groups among M memory groups to store input data in a rotated fashion;
• and
• if a damaged address location in one of the data groups is found:
• creating a repair entry in the address cache for the damaged address location with a last known correct data content in one logging group;
• and
• updating the repair entry in the address cache by updating the timestamp of the repair entry to prevent contents in the repair entry from being flushed to the damaged address location.