High throughput DRAM with distributed column access
AssigneeMicron Technology, Inc.
InventorYuan He
Life of this patent
Estimating the term…
Abstract
An apparatus having memory dies with a memory cell array divided into a plurality of data segments. A stagger circuit selects a common command signal and sets a column access signal to select a data segment to be accessed based on the common command signal and/or an individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment. A data bus connects the memory cell arrays to form data units with each data unit including a data segment from each memory cell array and configured such that the data segments are connected in parallel to the data bus and use a same line of the data bus. The stagger circuits are configured such that data segments identified for activation in the plurality of memory dies are not part of a same data unit.
Claims23
An apparatus, comprising:
- a plurality of memory dies, each memory die having,
- at least one memory cell array divided into a plurality of data segments that are configured to be selectively accessed, and
- a stagger circuit configured to select a common command signal from a plurality of common command signals and configured to set at least one of a column access signal or an individual command signal, the column access signal to select a data segment to be accessed based on the common command signal and the individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment;
- a data bus connecting each of the at least one memory cell arrays to form a plurality of data units, each data unit including a data segment from each memory cell array, wherein the data segments in each data unit are connected in parallel to the data bus and use a same line of the data bus;
- and
- a command signal circuit connected to each stagger circuit in the plurality of memory dies and configured to generate the plurality of common command signals,
- wherein the stagger circuits are further configured such that the selected data segments are not part of a same data unit.
An apparatus, comprising:
- a first memory die including a first memory cell array divided, at least in part, into a first data segment and a second data segment;
- a second memory die stacked with the first memory die, the second memory die including a second memory cell array divided, at least in part, into a third data segment and a fourth data segment;
- a first data bus coupled in common to the first data segment of the first memory die and the third data segment of the second memory die;
- and
- a second data bus coupled in common to the second data segment of the first memory die and the fourth data segment of the second memory die;
- wherein the first memory die is configured to simultaneously transfer memory data from the first data segment to the first data bus when the second memory die transfers memory data from the fourth data segment to the second data bus, and
- wherein the first data bus is separate and distinct from the second data bus, the first data segment is separate from the second data segment, and the third data segment is separate from the fourth data segment.
Dependencies are inferred from the claim text.