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US 11,237,620 B2Granted
Hierarchical power management unit for low power and low duty cycle devices
AssigneeIntel Corporation
InventorsDileep J. Kurian, Pranjali S. Deshmukh, Sriram Kabisthalam Muthukumar, Ankit Gupta, Tanay Karnik, David Arditti Ilitzky, Saurabh Bhandari
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Abstract
An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.
Claims20
An apparatus comprising:
- a first Power Management Unit (PMU);
- and
- a second PMU, wherein the second PMU is to decide to pause or abort one or more pending tasks, and to return control to the first PMU, to enable the first PMU to transition the apparatus to a low power state.
A system comprising:
- a battery;
- a memory:
- a processor coupled to the memory and the battery;
- and
- an antenna communicatively coupled to the processor, wherein the processor comprises:
- a first Power Management Unit (PMU);
- and
- a second PMU, wherein the second PMU is to decide to pause or abort one or more pending tasks, and to return control to the first PMU, to enable the first PMU to transition the processor to a low power state.
5 more elements
An apparatus comprising:
- a first die comprising a first Power Management Unit (PMU);
- and a second die comprising a second PMU,
- wherein the first die is to consume relatively less power compared to the second die;
- and
- wherein the second PMU is to decide to pause or abort one or more pending tasks, and to return control to the first PMU, to enable the first PMU to transition the apparatus to a low power state.
2 more elements
Dependencies are inferred from the claim text.