Back to results
US 11,237,619 B2Granted
Power gating system and electronic system including the same
AssigneeSK hynix Inc.
InventorWoongrae Kim
Life of this patent
Estimating the term…
Abstract
A power gating system may include a logic circuit area configured to perform a power-down operation according to at least one power-down control signal. The power gating system may also include a power gating control circuit configured to generate the at least one power-down control signal when a power-down request period is equal to or greater than a preset time according to a power-down mode signal.
Claims25
A power gating system comprising:
- a logic circuit area configured to perform a power-down operation according to at least one power-down control signal;
- a power gating control circuit configured to generate the at least one power-down control signal when a power-down request period is equal to or greater than a preset time according to a power-down mode signal;
- and
- a command decoder configured to generate the power-down mode signal by decoding a chip select signal and a command/address signal inputted from an external source.
1 more element
A power gating system comprising:
- a logic circuit area divided into a first area and a second area, the logic circuit area configured to perform a power-down operation for the first area according to a first power-down control signal of a plurality of power-down control signals and configured to perform the power-down operation for the second area according to a third power-down control signal of the plurality of power-down control signals;
- and
- a power gating control circuit configured to activate the third power-down control signal later than the first power-down control signal when a power-down request period according to a power-down mode signal is equal to or more than a preset time.
A power gating system comprising:
- a logic circuit area, including a plurality of logic circuit blocks, divided into a first area and a second area and configured to perform a power-down operation for the first area and the second area and perform a floating prevention operation for logic circuit blocks not subject to the power-down operation among the plurality of logic circuit blocks, according to first, second, third, and fourth power-down control signals;
- and
- a power gating control circuit configured to generate the first, second, third, and fourth power-down control signals with a time difference, wherein a period of the floating prevention operation includes a period of the power-down operation, when a power-down request period according to a power-down mode signal is equal to or more than a preset time.
An electronic system comprising:
- a processor configured to generate a power-down command by using a chip select signal and a command/address signal;
- and
- a semiconductor memory including a logic circuit area divided into a first area and a second area and configured to perform a power-down operation for the first area and the second area with a time difference when a power-down period according to the power-down command is equal to or greater than a preset time.
Dependencies are inferred from the claim text.