Arbitration techniques for managed memory

A NAND memory system comprising:

• multiple memory die;
• a memory controller coupled to the multiple memory die with one or more channels, the memory controller configured to receive multiple memory requests and service the memory requests using the multiple memory die within a power budget;
• wherein the memory controller includes power management circuitry configured to perform operations comprising:
• enabling a first subset of the multiple memory die of the NAND memory system;
• starting an active timer for each of the memory die in the first subset;
• disabling a second subset of multiple memory die of the NAND memory system, the second subset including a first memory die;
• starting an inactive timer for each die of the second subset of memory die of the NAND memory system;
• receiving a first memory request for a first memory access operation at the power management circuitry, the first memory access operation corresponding to a location within a first portion of the NAND memory system, the first portion including the first die, the first memory request comprising a read request or a write request;
• determining that the first memory request is for an inactive die;
• responsive to determining that the first memory request is for the inactive die, buffering the first memory request;
• determining that an inactive timer for the first memory die has expired;
• responsive to determining that the inactive timer for the first memory die has expired, determining that a second memory die has an active timer that is a longest pending active timer of all other memory die in the enabled subset;
• responsive to determining that the second memory die has the longest pending active timer, deactivating the second memory die and activating the first memory die;
• and
• responsive to activating the first memory die:
• retrieving the buffered first memory request;
• splitting the first memory request into a plurality of component operations selected from a set of possible component operations based upon a type of the first memory request, the set of possible component operations comprising sense, program, transfer to NAND, transfer from NAND, and erase operations;
• determining a first power load corresponding to performing a first component operation of the plurality of component operations;
• determining whether a sum of the first power load and a current power consumption exceeds a budgeted power consumption for the first die;
• and
• responsive to determining that the sum of the first power load and the current power consumption does not exceed the budgeted power consumption, executing the first component operation of the plurality of component operations.

A non-transitory machine-readable medium including instructions for power management of a NAND memory system, the instructions, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:

• enabling a first subset of multiple memory die of a NAND memory system;
• starting an active timer for each of the memory die in the first subset;
• disabling a second subset of multiple memory die of the NAND memory system, the second subset including a first memory die;
• starting an inactive timer for each die of the second subset of memory die of the NAND memory system;
• receiving a first memory request for a first memory access operation at power management circuitry of the NAND memory system, the first memory access operation corresponding to a location within a first portion of the memory system, the first portion including the first die, the first memory request comprising a read request or a write request;
• determining that the first memory request is for an inactive die;
• responsive to determining that the first memory request is for the inactive die, buffering the first memory request;
• determining that an inactive timer for the first memory die has expired;
• responsive to determining that the inactive timer for the first memory die has expired, determining that a second memory die has an active timer that is a longest pending active timer of all other memory die in the enabled subset;
• responsive to determining that the second memory die has the longest pending active timer, deactivating the second memory die and activating the first memory die;
• and
• responsive to activating the first memory die:
• retrieving the buffered first memory request;
• splitting the first memory request into a plurality of component operations selected from a set of possible component operations based upon a type of the first memory request, the set of possible component operations comprising sense, program, transfer to NAND, transfer from NAND, and erase operations;
• determining a first power load corresponding to performing a first component operation of the plurality of component operations;
• determining whether a sum of the first power load and a current power consumption exceeds a budgeted power consumption for the first portion of the memory system;
• and
• responsive to determining that the sum of the first power load and the current power consumption does not exceed the budgeted power consumption, executing the first component operation of the plurality of component operations.