On-chip clock controller (OCC) manager based turbo capture clocking
AssigneeQUALCOMM Incorporated
InventorsPunit Kishore, Ankit Goyal, Srinivas Patil
Life of this patent
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Abstract
Aspects of the disclosure are directed to clock management. In accordance with one aspect, a clock management apparatus for built-in self-test (BIST) circuitry includes a plurality of local clock controllers; a plurality of clock generators coupled to the plurality of local clock controllers; a master clock controller coupled to the plurality of clock generators; an X-tolerant logical built-in self test (XLBIST) circuit coupled to the master clock controller; and a test access port (TAP) coupled to the XLBIST circuit.
Claims30
A clock management apparatus for built-in self-test (BIST) circuitry, comprising
- a plurality of local clock controllers;
- a master clock controller coupled to the plurality of local clock controllers;
- a plurality of clock generators coupled to the master clock controller;
- an X-tolerant logical built-in self test (XLBIST) circuit coupled to the master clock controller;
- and
- a test access port (TAP) coupled to the XLBIST circuit.
A method for clock management for a built-in self-test (BIST) circuitry comprising:
- managing one or more clock activation signals for a plurality of clock generators using a plurality of time slots within a capture window and a plurality of time delays within each of the plurality of time slots;
- and
- generating a plurality of clocks using the plurality of clock generators.
An apparatus for clock management for a built-in self-test (BIST) circuitry comprising:
- means for managing one or more clock activation signals for a plurality of clock generators using a plurality of time slots within a capture window and a plurality of time delays within each of the plurality of time slots;
- and
- means for generating a plurality of clocks using the plurality of clock generators.
A non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement a clock management for a built-in self-test (BIST) circuitry, the computer executable code comprising:
- instructions for causing a computer to manage one or more clock activation signals for a plurality of clock generators using a plurality of time slots within a capture window and a plurality of time delays within each of the plurality of time slots;
- and
- instructions for causing the computer to generate a plurality of clocks using the plurality of clock generators.
Dependencies are inferred from the claim text.