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US 11,237,585 B2Granted
Self-biased current trimmer with digital scaling input
AssigneeMarvel Asia Pte Ltd
InventorCarlos Dorta-Quiñones
Life of this patent
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Abstract
In an embodiment, a circuit provided by the present invention includes a transistor connected to allow current to flow from a voltage supply to an output port. The circuit further includes a resistance ladder digital-to-analog converter (RDAC) configured to receive a digital input that indicates a voltage scaling factor. The RDAC is further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA). The circuit further includes an amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA), and a non-inverting input connected to the output port of the first transistor.
Claims21
A circuit comprising:
- a first transistor connected to allow current to flow from a voltage supply to an output port;
- a resistance ladder digital-to-analog converter (RDAC) configured to receive a digital input that indicates a voltage scaling factor, the RDAC further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA);
- a first amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA) from the RDAC, and a non-inverting input connected to the output port of the first transistor;
- a second amplifier having an inverting input port receiving a reference voltage (VREF), and a non-inverting input port connected to the input voltage port of the RDAC, such that VB is equal to VREF;
- a second transistor connected to allow current to flow from the voltage supply to the voltage input port of the RDAC, and further having a gate that is connected to receive an output of the second amplifier;
- a third transistor configured to allow current to flow from the voltage supply to a bias current port of the first amplifier;
- a fourth transistor;
- and
- a startup circuit configured to output a signal to the gates of the first, third, and fourth transistor.
6 more elements
A method of designing a chip, the method comprising:
- providing an initial design of the chip, the design including a first transistor and a resistance ladder configured to trim a reference voltage based on a programmable input;
- fabricating a physical chip based on the initial design of the chip;
- testing the chip to determine whether output currents are correct;
- and
- if output currents are incorrect, adjusting the programmable input to the resistance ladder to correct the output currents;
- wherein the first transistor is connected to allow current to flow from a voltage supply to an output port;
- wherein the resistance ladder is configured to receive a digital input that indicates a voltage scaling factor, the resistance ladder further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA);
- wherein a first amplifier includes an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA) from the resistance ladder, and a non-inverting input directly connected to the output port of the first transistor, a second amplifier includes an inverting input port receiving a reference voltage (VREF), and a non-inverting input port connected to the input voltage port of an RDAC, such that VB is equal to VREF, and a second transistor is connected to allow current to flow from the voltage supply to the voltage input port of the RDAC, and further having a gate that is connected to receive an output of the second amplifier;
- wherein a startup circuit is configured to output a signal to the gates of the first transistor, a third transistor, and a fourth transistor, the third transistor configured to allow current to flow from the voltage supply to a bias current port of the first amplifier.
6 more elements
A method comprising:
- allowing current to flow through a first transistor from a voltage supply to an output port;
- producing an output voltage (VA) at a resistance ladder, based on a digital input that indicates a voltage scaling factor, and an input voltage (VB) received at a voltage input port of the resistance ladder;
- receiving the output voltage (VA) from the resistance ladder at an inverting input port of a first amplifier having an output port connected to a gate of the first transistor, wherein the non-inverting input is directly connected to the output port;
- receiving a reference voltage (VREF) at an inverting input port of a second amplifier, a non-inverting input port of the second amplifier connected to the input voltage port of the resistance ladder, such that VB is equal to VREF;
- allowing current flow through a second transistor from the voltage supply to the voltage input port of the resistance ladder, wherein the second transistor has a gate that is connected to receive an output of the second amplifier;
- and
- outputting a signal from a startup circuit to the gates of the first transistor, a third transistor, and a fourth transistor, wherein the third transistor is configured to allow current to flow from the voltage supply to a bias current port of the first amplifier.
4 more elements
A system for designing a chip, the system comprising:
- a circuit having an initial design including a first transistor and a resistance ladder configured to trim a reference voltage based on a programmable input, wherein the chip is configured to allow for testing the chip to determine whether output currents are correct, and if output currents are incorrect, enabling user adjustment of the programmable input to the resistance ladder to correct the output currents;
- wherein the first transistor of the circuit is connected to allow current to flow from a voltage supply to an output port;
- wherein the resistance ladder is configured to receive a digital input that indicates a voltage scaling factor, the resistance ladder further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA);
- wherein a first amplifier includes an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA) from the resistance ladder, and a non-inverting input directly connected to the output port of the first transistor, a second amplifier includes an inverting input port receiving a reference voltage (VREF), and a non-inverting input port connected to the input voltage port of an RDAC, such that VB is equal to VREF, and a second transistor is connected to allow current to flow from the voltage supply to the voltage input port of the RDAC, and further having a gate that is connected to receive an output of the second amplifier;
- wherein a startup circuit is configured to output a signal to the gates of the first transistor, a third transistor, and a fourth transistor, wherein the third transistor is configured to allow current to flow from the voltage supply to a bias current port of the first amplifier.
2 more elements
A circuit comprising:
- a first transistor connected to allow current to flow from a voltage supply to an output port;
- a resistance ladder digital-to-analog converter (RDAC) configured to receive a digital input that indicates a voltage scaling factor, the RDAC further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA);
- a first amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA) from the RDAC, and a non-inverting input connected to the output port of the first transistor;
- a second amplifier having an inverting input port receiving a reference voltage (VREF), and a non-inverting input port connected to the input voltage port of the RDAC, such that VB is equal to VREF;
- a second transistor connected to allow current to flow from the voltage supply to the voltage input port of the RDAC, and further having a gate that is connected to receive an output of the second amplifier;
- a third transistor;
- a fourth transistor configured to allow current to flow from the voltage supply to a bias current port of the second amplifier;
- and
- a startup circuit configured to output a signal to the gates of the first, third, and fourth transistor.
6 more elements
A method comprising:
- allowing current to flow through a first transistor from a voltage supply to an output port;
- producing an output voltage (VA) at a resistance ladder, based on a digital input that indicates a voltage scaling factor, and an input voltage (VB) received at a voltage input port of the resistance ladder;
- receiving the output voltage (VA) from the resistance ladder at an inverting input port of a first amplifier having an output port connected to a gate of the first transistor, wherein the non-inverting input is directly connected to the output port;
- receiving a reference voltage (VREF) at an inverting input port of a second amplifier, a non-inverting input port of the second amplifier connected to the input voltage port of the resistance ladder, such that VB is equal to VREF;
- allowing current flow through a second transistor from the voltage supply to the voltage input port of the resistance ladder, wherein the second transistor has a gate that is connected to receive an output of the second amplifier;
- and
- outputting a signal from a startup circuit to the gates of the first transistor, a third transistor, and a fourth transistor, wherein the fourth transistor is configured to allow current to flow from the voltage supply to a bias current port of the second amplifier.
4 more elements
A method of designing a chip, the method comprising:
- providing an initial design of the chip, the design including a first transistor and a resistance ladder configured to trim a reference voltage based on a programmable input;
- fabricating a physical chip based on the initial design of the chip;
- testing the chip to determine whether output currents are correct;
- and
- if output currents are incorrect, adjusting the programmable input to the resistance ladder to correct the output currents;
- wherein the first transistor is connected to allow current to flow from a voltage supply to an output port;
- wherein the resistance ladder is configured to receive a digital input that indicates a voltage scaling factor, the resistance ladder further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA);
- wherein a first amplifier includes an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA) from the resistance ladder, and a non-inverting input directly connected to the output port of the first transistor, a second amplifier includes an inverting input port receiving a reference voltage (VREF), and a non-inverting input port connected to the input voltage port of an RDAC, such that VB is equal to VREF, and a second transistor is connected to allow current to flow from the voltage supply to the voltage input port of the RDAC, and further having a gate that is connected to receive an output of the second amplifier;
- wherein a startup circuit is configured to output a signal to the gates of the first transistor, a third transistor, and a fourth transistor, the fourth transistor configured to allow current to flow from the voltage supply to a bias current port of the second amplifier.
6 more elements
A system for designing a chip, the system comprising:
- a circuit having an initial design including a first transistor and a resistance ladder configured to trim a reference voltage based on a programmable input, wherein the chip is configured to allow for testing the chip to determine whether output currents are correct, and if output currents are incorrect, enabling user adjustment of the programmable input to the resistance ladder to correct the output currents;
- wherein the first transistor of the circuit is connected to allow current to flow from a voltage supply to an output port;
- wherein the resistance ladder is configured to receive a digital input that indicates a voltage scaling factor, the resistance ladder further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA);
- wherein a first amplifier includes an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA) from the resistance ladder, and a non-inverting input directly connected to the output port of the first transistor, a second amplifier includes an inverting input port receiving a reference voltage (VREF), and a non-inverting input port connected to the input voltage port of an RDAC, such that VB is equal to VREF, and a second transistor is connected to allow current to flow from the voltage supply to the voltage input port of the RDAC, and further having a gate that is connected to receive an output of the second amplifier;
- wherein a startup circuit is configured to output a signal to the gates of the first transistor, a third transistor, and a fourth transistor, the fourth transistor configured to allow current to flow from the voltage supply to a bias current port of the second amplifier.
2 more elements
Dependencies are inferred from the claim text.