Pixel structure and manufacturing method thereof, array substrate and display device

A manufacturing method of a pixel structure, comprising:

• forming a signal line and a common electrode line which are spaced apart from each other on a support substrate;
• forming a transistor on the support substrate, wherein the transistor comprises a semiconductor layer, and the semiconductor layer comprises a source region and a drain region;
• forming a first storage electrode on the support substrate, wherein the first storage electrode is insulated from the common electrode line and is connected with the drain region of the semiconductor layer;
• and
• forming a second storage electrode on the support substrate, and the second storage electrode is connected with the common electrode line, protrudes from the common electrode line towards the signal line, and is insulated from the first storage electrode,
• wherein an entirety of an orthographic projection of the second storage electrode on the support substrate is all located between an orthographic projection of the signal line on the support substrate and an edge of an orthographic projection of the common electrode line on the support substrate close to the signal line, an entirety of an orthographic projection of the portion of the first storage electrode on the support substrate and an entirely of an orthographic projection of the portion, which overlaps the portion of the first storage electrode, of the second storage electrode on the support substrate are between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line, to form a first storage capacitance between the first storage electrode and the second storage electrode,
• an entirety of an orthographic projection of the first storage capacitance on the support substrate is all located between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line, the orthographic projection of the first storage capacitance on the support substrate does not include a portion provided outside a region between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line;
• the manufacturing method of the pixel structure further comprises:
• forming a third storage electrode on the support substrate, wherein the third storage electrode is connected with the first storage electrode and is insulated from the second storage electrode, and the third storage electrode overlaps the second storage electrode to form a third storage capacitance, and
• an entirety of orthographic projections of portions, which overlap each other, of the third storage electrode and the second storage electrode on the support substrate are at least between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line.

A pixel structure, comprising:

• a support substrate;
• a semiconductor film provided on the support substrate, wherein the semiconductor film comprises a semiconductor layer and a first storage electrode, the semiconductor layer comprises a source region and a drain region, and the first storage electrode and the semiconductor layer are formed integrally;
• and
• a conducting layer provided at a side of the semiconductor film facing away from the support substrate, wherein the conducting layer comprises a signal line, a common electrode line, and a second storage electrode, the common electrode line is insulated from the first storage electrode, the second storage electrode is connected with the common electrode line, protrudes from the common electrode line towards the signal line, and is insulated from the first storage electrode, the conducting layer further comprises a gate electrode, an extension direction of the common electrode line and an extension direction of the signal line are same as each other, the second storage electrode and the common electrode line are formed integrally,
• wherein each of the first storage electrode and the second storage electrode comprises a portion between the signal line and an edge of the common electrode line close to the signal line, an entirety of an orthographic projection of the second storage electrode on the support substrate is all located between an orthographic projection of the signal line on the support substrate and an edge of an orthographic projection of the common electrode line on the support substrate close to the signal line, and the portion of the first storage electrode overlaps the portion of the second storage electrode to form a first storage capacitance between the first storage electrode and the second storage electrode, and
• an entirety of an orthographic projection of the first storage capacitance on the support substrate is all located between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line, the orthographic projection of the first storage capacitance on the support substrate does not include a portion provided outside a region between the orthographic projection of the signal line on the support substrate and the orthographic projection of the common electrode line on the support substrate;
• the pixel structure further comprises:
• a third storage electrode on the support substrate, wherein the third storage electrode is connected with the first storage electrode and is insulated from the second storage electrode, and the third storage electrode overlaps the second storage electrode to form a third storage capacitance, and
• an entirety of orthographic projections of portions, which overlap each other, of the third storage electrode and the second storage electrode on the support substrate are at least between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line.