Layout-aware test pattern generation and fault detection
AssigneeSynopsys, Inc.
InventorsAlodeep Sanyal, Girish A. Patankar, Rohit Kapur, Salvatore Talluto
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AssigneeSynopsys, Inc.
InventorsAlodeep Sanyal, Girish A. Patankar, Rohit Kapur, Salvatore Talluto
Estimating the term…
Methods and apparatuses to assign faults to nets in an integrated circuit (IC) are described. Each net comprises a drive pin, a set of load pins, and a fan-out structure that electrically couples the drive pin to the set of load pins. During operation, a fan-out structure of a net can be partitioned into a set of non-overlapping subnets and a set of branch nodes, wherein each branch node electrically couples three or more non-overlapping subnets. Next, each branch node can be represented by using a subnet primitive, wherein each subnet primitive comprises three or more pins that are electrically coupled to non-overlapping subnets that are electrically coupled by the branch node. A fault can then be assigned to a pin of a subnet primitive that is electrically coupled to a non-overlapping subnet, thereby modeling the fault in the non-overlapping subnet.
A method for assigning faults to nets in an integrated circuit (IC), wherein each net comprises a drive pin, a set of load pins, and a fan-out structure that electrically couples the drive pin to the set of load pins, the method comprising:
A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for assigning faults to nets in an integrated circuit (IC), wherein each net comprises a drive pin, a set of load pins, and a fan-out structure that electrically couples the drive pin to the set of load pins, the method comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.