Test array structure, wafer structure and wafer testing method

A test array structure, comprising:

• a substrate;
• a first cell and a second cell, wherein each of the first and second cells has a first drain region, a first gate region, a source region, a second gate region and a second drain region connected together in sequence;
• a first bit-line ring and a second bit-line ring located on the substrate, wherein the first drain region and the first gate region of the first cell are located within the first bit-line ring, the second drain region and the second gate region of the first cell is located between the first and second bit-line rings, the first drain region and the first gate region of the second cell is located within the second bit-line ring, and the second drain region and the second gate region of the second cell is located beyond the first and second bit-line rings;
• and
• a first word-line, a second word-line, a third word-line and a fourth word-line located over the first and second bit-line rings, wherein the second drain region of the first cell and the first drain region of the second cell is located between the second and third word-lines.