Gate drive unit and driving method thereof and gate drive circuit

A driving method of a gate drive unit, the gate drive unit comprising a shift register and a plurality of output control modules connected to the shift register, each of the plurality of output control modules connected to a clock scanning signal line and a first scanning signal output terminal corresponding to the output control module, respectively, wherein

• each of the plurality of output control modules comprises a first output control submodule and an output reset submodule,
• the first output control submodule is connected to a signal output terminal of the shift register, the clock scanning signal line corresponding to the output control module, and the first scanning signal output terminal corresponding to the output control module, respectively, and the first output control submodule is configured to send a clock scanning signal of the clock scanning signal line to the first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register, and
• the output reset submodule is connected to a pull-down node of the shift register and the first scanning signal output terminal, respectively, and the output reset submodule is configured to reset a first scanning signal outputted by the first scanning signal output terminal, under control of a potential of the pull-down node of the shift register,
• the driving method comprises:
• in an output period, outputting, by the signal output terminal of the shift register, an effective electric level, sending, by the first output control submodule of each of the plurality of output control modules, the clock scanning signal of the clock scanning signal line to the first scanning signal output terminal;
• and
• in a reset period, under control of the potential of the pull-down node of the shift register, resetting, by the output reset submodule, the first scanning signal outputted by the first scanning signal output terminal;
• wherein each of the plurality of output control modules further comprises a second output control submodule;
• the second output control submodule is connected to a second scanning signal output terminal corresponding to the output control module and the first scanning signal output terminal, respectively;
• and the second output control submodule is configured to provide a second scanning signal having a reversed phase with respective to the first scanning signal to the second scanning signal output terminal, under control of the first scanning signal outputted by the first scanning signal output terminal;
• wherein the second output control submodule comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor;
• a control terminal and a first terminal of the third transistor are connected to a second power supply, and a second terminal of the third transistor is connected to both of a first terminal of the fourth transistor and a control terminal of the fifth transistor;
• a control terminal of the fourth transistor is connected to the first scanning signal output terminal, and a second terminal of the fourth transistor is connected to the first power supply;
• a first terminal of the fifth transistor is connected to a third power supply, and a second terminal of the fifth transistor is connected to the second scanning signal output terminal;
• and a control terminal of the sixth transistor is connected to the first scanning signal output terminal, a first terminal of the sixth transistor is connected to a fourth power supply, and a second terminal of the sixth transistor is connected to the second scanning signal output terminal;
• and
• wherein the sixth transistor comprises a substrate, a first gate, an active layer, and a second gate;
• the first gate is located on a side of the active layer facing the substrate, and the second gate is located on a side of the active layer facing away from the substrate;
• and the first gate and second gate are connected to the first scanning signal output terminal and the second scanning signal output terminal via gate lines, respectively.