Back to results
US 11,232,845 B2Granted
Nonvolatile memory device and method of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsMyoung-Won Yoon, Sang-Hyun Joo
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory device includes a memory block with an unused line connected to dummy cells and used lines connected to normal cells, and a controller which applies an erase voltage to the memory block, applies an unused line erase voltage to the unused line, and applies a word line erase voltage to the used lines during an erase operation. The dummy cells are not programmed during a program operation while the normal cells are programmed, the unused line erase voltage transits from a first voltage to a floating voltage at a first time point, and the controller reads the dummy cells and controls at least one of the magnitude of the first voltage and the first time point based on the result of reading the dummy cells.
Claims20
A nonvolatile memory device comprising:
- a memory block disposed on a substrate, the memory block including a first unused line connected to a plurality of first dummy memory cells, and a plurality of used lines connected to a plurality of normal memory cells, wherein the nonvolatile memory device is configured such that the plurality of first dummy memory cells are not programmed during a program operation which is performed on the plurality of normal memory cells;
- and
- a controller configured to perform an erase operation on the memory block, wherein the controller, in the erase operation, causes:
- a substrate voltage to be applied to the substrate on which the memory block is disposed,
- a first unused line erase voltage to be applied to the first unused line, and
- a word line erase voltage to be applied to the plurality of used lines,
- wherein during application of the substrate voltage to the substrate, the substrate voltage starts to increase from a first substrate voltage level toward a second substrate voltage level at a reference time point,
- wherein during application of the first unused line erase voltage to the first unused line, the first unused line erase voltage transits from a first voltage level to a floating voltage at a first time point after the reference time point, and
- wherein the controller is further configured to read the plurality of erased first dummy memory cells and to control at least one of the magnitude of the first voltage level and the first time point based on the result of reading the plurality of erased first dummy memory cells.
6 more elements
A nonvolatile memory device comprising:
- a memory block disposed on a substrate,
- wherein the memory block comprises a first unused line connected to a plurality of first dummy memory cells and a plurality of used lines connected to a plurality of normal memory cells, and
- wherein the nonvolatile memory device is configured such that the plurality of first dummy memory cells are not programmed during a program operation which is performed on the plurality of normal memory cells;
- and
- a controller configured to:
- determine, in response to an erase command, whether the plurality of first dummy memory cells have deteriorated by reading the plurality of first dummy memory cells;
- and
- cause, in response to the determining of the plurality of first dummy memory cells having deteriorated, a first unused line erase voltage to be applied to the first unused line to perform an erase operation on the plurality of first dummy memory cells,
- wherein during application of the first unused line erase voltage to the first unused line, the first unused line erase voltage transits from a first voltage level to a floating voltage at a first time point after a reference time point when a substrate voltage which the controller, in response to the erase command, causes to be applied to the substrate, starts to increase from a first substrate voltage level toward a second substrate voltage level.
6 more elements
A nonvolatile memory device comprising:
- a memory cell array comprising a memory block in which a ground select line connected to a plurality of ground select transistors, a first dummy word line connected to a plurality of first dummy memory cells, a plurality of word lines connected to a plurality of normal memory cells, a second dummy word line connected to a plurality of second dummy memory cells and a string select line connected to a plurality of string select transistors are sequentially stacked;
- and
- a controller configured to:
- receive an erase command;
- read a plurality of threshold voltages of the plurality of ground select transistors, the plurality of first dummy memory cells, the plurality of string select transistors and the plurality of second dummy memory cells in response to the erase command;
- determine a short-term erase voltage to be applied to each of the string select line, the ground select line, the first dummy word line and the second dummy word line during an erase operation according to the erase command based on the result of reading the plurality of threshold voltages;
- and
- apply the short-term erase voltage to each of the ground select line, the first dummy word line, the second dummy word line and the string select line during the erase operation while a word line erase voltage is applied to the plurality of word lines.
5 more elements
Dependencies are inferred from the claim text.