Memory with adaptive slow-cell data compression

A memory device comprising:

• a memory cell array;
• a data circuit configured to receive a first write data unit including a first plurality of data bits;
• a row decoder connected to the memory cell array and configured to select a first word-line connected to a first plurality of memory cells of the memory cell array;
• a page buffer connected to the data circuit and to the memory cell array and configured to program by at least one pulse the first plurality of data bits to the first plurality of memory cells;
• a counter configured to determine if a number of cells successfully programmed by the at least one pulse is less than a threshold;
• a slow-cell data compressor connected to the counter and configured to compress, if the number of cells successfully programmed by the at least one pulse is less than the threshold, a first sparse vector of unsuccessfully programmed data bits;
• and
• a control circuit connected to the slow-cell data compressor and to the page buffer, and configured to concatenate, if the number of cells successfully programmed by the at least one pulse is less than the threshold, the first sparse vector based on a second write data unit, and to write the concatenated vector to a second plurality of memory cells of the memory cell array connected to a second word-line different from the first word-line,
• wherein the page buffer is configured to read the compressed vector from the second plurality of memory cells, and to decompress the vector.

A program storage device tangibly embodying a non-transitory program of instructions executable by a processor to implement steps of memory programming, the steps comprising:

• receiving a first write data unit including a plurality of data bits;
• selecting a first address line connected to a plurality of memory cells;
• programming by at least one pulse the plurality of data bits to the plurality of memory cells;
• determining if a number of cells successfully programmed by the at least one pulse is less than a threshold;
• and
• if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, selecting a second address line connected to another plurality of memory cells, and programming the concatenated vector to the other plurality of memory cells,
• wherein the first and second address lines are disposed on different levels of a three-dimensional memory.