US 11,232,843 B2Granted

Nonvolatile semiconductor storage device and method for performing a read operation on the same

AssigneeKioxia Corporation

InventorsHidehiro Shiga, Takashi Maeda

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Abstract

A nonvolatile semiconductor storage device includes a first channel layer including a first drain-side select transistor, a first source-side select transistor, and a first memory cell transistor, a second channel layer including a second drain-side select transistor, a second source-side select transistor, and a second memory cell transistor, a word line that functions as a gate electrode of the first and second memory cell transistors, and a controller. When a read operation is executed on the first memory cell transistor, the controller turns on the second drain-side select transistor and the second source-side select transistor, supplies a first voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and then, supplies a second voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned on.

Claims20

Dependent claims

A nonvolatile semiconductor storage device comprising:

a substrate having a main surface that extends in a first direction and a second direction crossing the first direction;
a bit line that extends in a third direction crossing the first and second directions;
a source line that extends in the third direction;
a first channel layer that is disposed on the one side of the substrate in the third direction, and includes a first drain-side select transistor that is connected to the bit line, a first source-side select transistor that is connected to the source line, and a first memory cell transistor connected between the first drain-side select transistor and the first source-side select transistor;
a second channel layer that is disposed on one side of the first channel layer in the third direction, and includes a second drain-side select transistor that is connected to the bit line, a second source-side select transistor connected to the source line, and a second memory cell transistor connected between the second drain-side select transistor and the second source-side select transistor;
a word line that is disposed on one side of the first channel layer and the second channel layer in the second direction, extends in the third direction, and functions as a gate electrode of the first memory cell transistor and the second memory cell transistor;
and
a controller,
wherein when a read operation is executed on the first memory cell transistor, the controller executes
a first operation to turn on the second drain-side select transistor and the second source-side select transistor, and simultaneously, supply at least one first read voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and
a second operation to supply at least one second read voltage to the word line in a state where at least the first drain-side select transistor and the first source-side select transistor are turned on, after the first operation.

8 more elements

A method of performing a read operation on a first memory cell transistor in a nonvolatile semiconductor storage device comprising:

a substrate having a main surface that extends in a first direction and a second direction crossing the first direction;
a bit line that extends in a third direction crossing the first and second directions;
a source line that extends in the third direction;
a first channel layer that is disposed on the one side of the substrate in the third direction, and includes a first drain-side select transistor that is connected to the bit line, a first source-side select transistor that is connected to the source line, and the first memory cell transistor connected between the first drain-side select transistor and the first source-side select transistor;
a second channel layer that is disposed on one side of the first channel layer in the third direction, and includes a second drain-side select transistor that is connected to the bit line, a second source-side select transistor connected to the source line, and a second memory cell transistor connected between the second drain-side select transistor and the second source-side select transistor;
and
a word line that is disposed on one side of the first channel layer and the second channel layer in the second direction, extends in the third direction, and functions as a gate electrode of the first memory cell transistor and the second memory cell transistor,
wherein said method includes
a first operation to turn on the second drain-side select transistor and the second source-side select transistor, and simultaneously, supply at least one first read voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and
a second operation to supply at least one second read voltage to the word line in a state where at least the first drain-side select transistor and the first source-side select transistor are turned on, after the first operation.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/009,376Filed 1 Sep 2020
Priority: JP JP2020-0370614 Mar 2020
Published: US 2021/0280257 A19 Sep 2021
Granted: 25 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits