Methods of operating memory devices based on sub-block positions and related memory system

A memory device comprising:

• a lower chip having a peripheral circuit region;
• a first upper chip stacked on the lower chip, bonded to the lower chip and having a first cell region;
• and
• a second upper chip stacked on the first upper chip, bonded to the first upper chip and having a second cell region,
• wherein the first cell region comprises:
• a first substrate formed adjacent to the second upper chip;
• a first common source line formed on a lower surface of the first substrate;
• a first metal layer formed adjacent to the lower chip and connected to a first bit line;
• and
• a first sub-block configured to perform a program operation in an alignment order of first selected word lines based on a direction from the first common source line to the first bit line, and
• wherein the second cell region comprises:
• a second substrate;
• a second common source line formed on a lower surface of the second substrate;
• a second metal layer formed adjacent to the first upper chip and connected to a second bit line;
• a second sub-block formed adjacent to the second metal layer and configured to perform a program operation in an alignment order of second selected word lines based on a direction from the second bit line to the second common source line;
• and
• a third sub-block formed adjacent to the second substrate and configured to perform a program operation in an alignment order of third selected word lines based on a third direction from the second common source line toward the second bit line.