Erasing method for 3D NAND flash memory
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsChanghyun Lee, Chao Zhang, Haibo Li
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Abstract
Embodiments of erasing methods for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes multiple decks vertically stacked over a substrate, wherein each deck includes a plurality of memory cells. The erasing method includes checking states of the plurality of memory cells of an erase-inhibit deck and preparing the erase-inhibit deck according to the states of the plurality of memory cells. The erasing method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase-inhibit deck, and applying a low voltage on selected word lines of a target deck.
Claims20
An erasing method for a three-dimensional (3D) memory device comprising multiple decks vertically stacked over a substrate, wherein each deck comprises a plurality of memory cells, the erasing method comprising:
- checking states of the plurality of memory cells of an erase-inhibit deck;
- preparing the erase-inhibit deck according to the states of the plurality of memory cells;
- applying an erase voltage at an array common source or an array cell well-body;
- applying a hold-release voltage on unselected word lines of the erase-inhibit deck;
- and
- applying a low voltage on selected word lines of a target deck, wherein the low voltage is less than the erase voltage.
A three-dimensional (3D) memory device, comprising:
- multiple decks vertically stacked over a substrate, wherein each deck comprises
- a film stack of alternating conductive and dielectric layers;
- and
- a plurality of memory strings penetrating through the film stack, each memory string comprising a plurality of memory cells;
- and
- a conductive plug disposed between adjacent decks, electrically connecting the plurality of memory strings between the adjacent decks,
- wherein the multiple decks comprise a target deck and an erase-inhibit deck, and the 3D memory device is configured to erase the target deck by:
- checking states of the plurality of memory cells of the erase-inhibit deck;
- preparing the erase-inhibit deck according to the states of the plurality of memory cells of the erase-inhibit deck;
- applying an erase voltage at an array common source or an array cell well-body;
- applying a hold-release voltage on unselected word lines of the erase-inhibit deck;
- and
- applying a low voltage on selected word lines of the target deck.
Dependencies are inferred from the claim text.