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US 11,232,838 B2Granted
Ferroelectric FET-based content addressable memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus Lu
Life of this patent
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Abstract
An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.
Claims20
A memory device, comprising:
- a first and second data storage units, each adapted to store one binary bit, each of data storage units including:
- a matchline (“ML”) switching transistor;
- and
- a serial combination of a ferroelectric field-effect transistor (“FeFET”) and an input switching transistor,
- the ML switching transistors of the first and second data storage units being connected to each other at a junction, forming a serial combination having a first end and a second end,
- one end of the serial combination of the FeFET and input switching transistor in the first data storage units being connected to the first end of the serial combination of the ML switching transistors at a junction, and one end of the serial combination of the FeFET and input switching transistor in the second data storage units being connected to the junction between the ML switching transistors.
3 more elements
A data processing device, comprising:
- a plurality of wordlines (“WLs”);
- a plurality of matchline-enable (“ML-enable”) lines;
- a plurality of bitlines (“BLs”);
- a plurality of selectlines (“SLs”);
- a plurality of inputlines (“INs”);
- a plurality of data storage units arranged logically in a plurality of rows and a plurality of columns, each of the rows of data storage units associated with a respective one of the WLs and respective one of the ML-enable lines, each of the columns of the data storage units associated with a respective one of the BLs, a respective one of the SLs and a respective one of the INs, each of the data storage units comprising:
- a matchline (“ML”) switching transistor;
- a ferroelectric field-effect transistor (“FeFET”);
- and
- an input switching transistor connected to the FeFET at a junction and forming a serial combination with the FeFET, the gate of the FeFET being connected to the associated WL;
- a first end of the serial combination being connected to the associated BL;
- the junction between the input switching transistor and FeFET being connected to the associated SL;
- the gate of the input switch transistor being connected to the associated IN;
- the ML switching transistors in each row of the data storage devices are connected to each other in series at the plurality of BLs, forming a matchline having an input end and an output end, the gates of the ML switching transistors in each row of the data storage devices are connected to the associated ML-enable line.
11 more elements
A data processing method, comprising:
- storing in a memory array a first set of values, each of which capable of representing alternatively a binary “0”, “1” and “X” (don't-care), the stored values thereby representing a first binary digital pattern;
- providing a second set of values, each corresponding to a respective one of the first set of values and being indicative of a binary “0”, “1” or “X”, the second set of values thereby representing a second binary digital pattern;
- comparing each of the first set of values with the corresponding one of the second set of values;
- and
- generating a signal indicative of a match between the first and second binary patterns if each value in the first set and the corresponding value in the second set are identical to each other, or at least one of the two values is indicative of an “X”;
- wherein storing a the first set values comprises storing a set of binary value pairs, wherein storing each of the binary value pair comprises writing the binary value pair to respective pairs of first and second data storage units in a memory device, each of data storage units including:
- a matchline (“ML”) switching transistor;
- and
- a serial combination of a ferroelectric field-effect transistor (“FeFET”) and an input switching transistor, each of the ML switching transistor, FeFET and input switching transistor having a gate, a source and a drain, and the FeFET having a threshold voltage for altering its memory state,
- the ML switching transistors of the first and second data storage units being connected to each other at a junction, forming a serial combination having a first end and a second end,
- one end of the serial combination of the FeFET and input switching transistor in the first data storage units being connected to the first end of the serial combination of the ML switching transistors at a junction, and one end of the serial combination of the FeFET and input switching transistor in the second data storage units being connected to the junction between the ML switching transistors.
8 more elements
Dependencies are inferred from the claim text.